1 /* 2 * Copyright 2004-2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 37 #define CONFIG_PCI1 1 /* PCI controller */ 38 #define CONFIG_PCIE1 1 /* PCIE controller */ 39 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 42 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #ifndef __ASSEMBLY__ 48 extern unsigned long get_clock_freq(void); 49 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 50 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 51 52 /* 53 * These can be toggled for performance analysis, otherwise use default. 54 */ 55 #define CONFIG_L2_CACHE /* toggle L2 cache */ 56 #define CONFIG_BTB /* toggle branch predition */ 57 58 /* 59 * Only possible on E500 Version 2 or newer cores. 60 */ 61 #define CONFIG_ENABLE_36BIT_PHYS 1 62 63 64 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 65 66 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 67 #define CONFIG_SYS_MEMTEST_END 0x00400000 68 69 /* 70 * Base addresses -- Note these are effective addresses where the 71 * actual resources get mapped (not physical addresses) 72 */ 73 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 74 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 75 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 76 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 77 78 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 79 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 80 81 /* DDR Setup */ 82 #define CONFIG_FSL_DDR2 83 #undef CONFIG_FSL_DDR_INTERACTIVE 84 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 85 #define CONFIG_DDR_SPD 86 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 88 89 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 90 91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 93 94 #define CONFIG_NUM_DDR_CONTROLLERS 1 95 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 96 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 97 98 /* I2C addresses of SPD EEPROMs */ 99 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 100 101 /* Make sure required options are set */ 102 #ifndef CONFIG_SPD_EEPROM 103 #error ("CONFIG_SPD_EEPROM is required") 104 #endif 105 106 #undef CONFIG_CLOCKS_IN_MHZ 107 108 /* 109 * Local Bus Definitions 110 */ 111 112 /* 113 * FLASH on the Local Bus 114 * Two banks, 8M each, using the CFI driver. 115 * Boot from BR0/OR0 bank at 0xff00_0000 116 * Alternate BR1/OR1 bank at 0xff80_0000 117 * 118 * BR0, BR1: 119 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 120 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 121 * Port Size = 16 bits = BRx[19:20] = 10 122 * Use GPCM = BRx[24:26] = 000 123 * Valid = BRx[31] = 1 124 * 125 * 0 4 8 12 16 20 24 28 126 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 127 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 128 * 129 * OR0, OR1: 130 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 131 * Reserved ORx[17:18] = 11, confusion here? 132 * CSNT = ORx[20] = 1 133 * ACS = half cycle delay = ORx[21:22] = 11 134 * SCY = 6 = ORx[24:27] = 0110 135 * TRLX = use relaxed timing = ORx[29] = 1 136 * EAD = use external address latch delay = OR[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 140 */ 141 #define CONFIG_SYS_BCSR_BASE 0xf8000000 142 143 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 144 145 /*Chip select 0 - Flash*/ 146 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 147 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 148 149 /*Chip slelect 1 - BCSR*/ 150 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 151 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 152 153 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 155 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 156 #undef CONFIG_SYS_FLASH_CHECKSUM 157 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 158 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 159 160 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 161 162 #define CONFIG_FLASH_CFI_DRIVER 163 #define CONFIG_SYS_FLASH_CFI 164 #define CONFIG_SYS_FLASH_EMPTY_INFO 165 166 167 /* 168 * SDRAM on the LocalBus 169 */ 170 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 171 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 172 173 174 /*Chip select 2 - SDRAM*/ 175 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 176 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 177 178 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 179 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 180 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 181 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 182 183 /* 184 * Common settings for all Local Bus SDRAM commands. 185 * At run time, either BSMA1516 (for CPU 1.1) 186 * or BSMA1617 (for CPU 1.0) (old) 187 * is OR'ed in too. 188 */ 189 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 190 | LSDMR_PRETOACT7 \ 191 | LSDMR_ACTTORW7 \ 192 | LSDMR_BL8 \ 193 | LSDMR_WRC4 \ 194 | LSDMR_CL3 \ 195 | LSDMR_RFEN \ 196 ) 197 198 /* 199 * The bcsr registers are connected to CS3 on MDS. 200 * The new memory map places bcsr at 0xf8000000. 201 * 202 * For BR3, need: 203 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 204 * port-size = 8-bits = BR[19:20] = 01 205 * no parity checking = BR[21:22] = 00 206 * GPMC for MSEL = BR[24:26] = 000 207 * Valid = BR[31] = 1 208 * 209 * 0 4 8 12 16 20 24 28 210 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 211 * 212 * For OR3, need: 213 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 214 * disable buffer ctrl OR[19] = 0 215 * CSNT OR[20] = 1 216 * ACS OR[21:22] = 11 217 * XACS OR[23] = 1 218 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 219 * SETA OR[28] = 0 220 * TRLX OR[29] = 1 221 * EHTR OR[30] = 1 222 * EAD extra time OR[31] = 1 223 * 224 * 0 4 8 12 16 20 24 28 225 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 226 */ 227 #define CONFIG_SYS_BCSR (0xf8000000) 228 229 /*Chip slelect 4 - PIB*/ 230 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 231 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 232 233 /*Chip select 5 - PIB*/ 234 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 235 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 236 237 #define CONFIG_SYS_INIT_RAM_LOCK 1 238 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 239 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 240 241 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 242 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 243 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 244 245 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 246 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 247 248 /* Serial Port */ 249 #define CONFIG_CONS_INDEX 1 250 #undef CONFIG_SERIAL_SOFTWARE_FIFO 251 #define CONFIG_SYS_NS16550 252 #define CONFIG_SYS_NS16550_SERIAL 253 #define CONFIG_SYS_NS16550_REG_SIZE 1 254 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 255 256 #define CONFIG_SYS_BAUDRATE_TABLE \ 257 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 258 259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 261 262 /* Use the HUSH parser*/ 263 #define CONFIG_SYS_HUSH_PARSER 264 #ifdef CONFIG_SYS_HUSH_PARSER 265 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 266 #endif 267 268 /* pass open firmware flat tree */ 269 #define CONFIG_OF_LIBFDT 1 270 #define CONFIG_OF_BOARD_SETUP 1 271 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 272 273 /* 274 * I2C 275 */ 276 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 277 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 278 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 279 #define CONFIG_I2C_MULTI_BUS 280 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 281 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 282 #define CONFIG_SYS_I2C_SLAVE 0x7F 283 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 284 #define CONFIG_SYS_I2C_OFFSET 0x3000 285 #define CONFIG_SYS_I2C2_OFFSET 0x3100 286 287 /* 288 * General PCI 289 * Memory Addresses are mapped 1-1. I/O is mapped from 0 290 */ 291 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 292 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 293 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 294 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 295 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 296 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 297 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 298 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 299 300 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 301 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 302 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 303 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 304 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 305 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 306 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 307 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 308 309 #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 310 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 311 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 312 313 #ifdef CONFIG_QE 314 /* 315 * QE UEC ethernet configuration 316 */ 317 #define CONFIG_UEC_ETH 318 #ifndef CONFIG_TSEC_ENET 319 #define CONFIG_ETHPRIME "FSL UEC0" 320 #endif 321 #define CONFIG_PHY_MODE_NEED_CHANGE 322 #define CONFIG_eTSEC_MDIO_BUS 323 324 #ifdef CONFIG_eTSEC_MDIO_BUS 325 #define CONFIG_MIIM_ADDRESS 0xE0024520 326 #endif 327 328 #define CONFIG_UEC_ETH1 /* GETH1 */ 329 330 #ifdef CONFIG_UEC_ETH1 331 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 332 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 333 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 334 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 335 #define CONFIG_SYS_UEC1_PHY_ADDR 7 336 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID 337 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 338 #endif 339 340 #define CONFIG_UEC_ETH2 /* GETH2 */ 341 342 #ifdef CONFIG_UEC_ETH2 343 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 344 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 345 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 346 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 347 #define CONFIG_SYS_UEC2_PHY_ADDR 1 348 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID 349 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 350 #endif 351 #endif /* CONFIG_QE */ 352 353 #if defined(CONFIG_PCI) 354 355 #define CONFIG_NET_MULTI 356 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 357 358 #undef CONFIG_EEPRO100 359 #undef CONFIG_TULIP 360 361 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 362 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 363 364 #endif /* CONFIG_PCI */ 365 366 #ifndef CONFIG_NET_MULTI 367 #define CONFIG_NET_MULTI 1 368 #endif 369 370 #if defined(CONFIG_TSEC_ENET) 371 372 #define CONFIG_MII 1 /* MII PHY management */ 373 #define CONFIG_TSEC1 1 374 #define CONFIG_TSEC1_NAME "eTSEC0" 375 #define CONFIG_TSEC2 1 376 #define CONFIG_TSEC2_NAME "eTSEC1" 377 378 #define TSEC1_PHY_ADDR 2 379 #define TSEC2_PHY_ADDR 3 380 381 #define TSEC1_PHYIDX 0 382 #define TSEC2_PHYIDX 0 383 384 #define TSEC1_FLAGS TSEC_GIGABIT 385 #define TSEC2_FLAGS TSEC_GIGABIT 386 387 /* Options are: eTSEC[0-1] */ 388 #define CONFIG_ETHPRIME "eTSEC0" 389 390 #endif /* CONFIG_TSEC_ENET */ 391 392 /* 393 * Environment 394 */ 395 #define CONFIG_ENV_IS_IN_FLASH 1 396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 397 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 398 #define CONFIG_ENV_SIZE 0x2000 399 400 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 401 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 402 403 404 /* 405 * BOOTP options 406 */ 407 #define CONFIG_BOOTP_BOOTFILESIZE 408 #define CONFIG_BOOTP_BOOTPATH 409 #define CONFIG_BOOTP_GATEWAY 410 #define CONFIG_BOOTP_HOSTNAME 411 412 413 /* 414 * Command line configuration. 415 */ 416 #include <config_cmd_default.h> 417 418 #define CONFIG_CMD_PING 419 #define CONFIG_CMD_I2C 420 #define CONFIG_CMD_MII 421 #define CONFIG_CMD_ELF 422 #define CONFIG_CMD_IRQ 423 #define CONFIG_CMD_SETEXPR 424 425 #if defined(CONFIG_PCI) 426 #define CONFIG_CMD_PCI 427 #endif 428 429 430 #undef CONFIG_WATCHDOG /* watchdog disabled */ 431 432 /* 433 * Miscellaneous configurable options 434 */ 435 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 436 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 437 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 438 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 439 #if defined(CONFIG_CMD_KGDB) 440 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 441 #else 442 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 443 #endif 444 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 445 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 446 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 447 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 448 449 /* 450 * For booting Linux, the board info and command line data 451 * have to be in the first 16 MB of memory, since this is 452 * the maximum mapped by the Linux kernel during initialization. 453 */ 454 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 455 456 /* 457 * Internal Definitions 458 * 459 * Boot Flags 460 */ 461 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 462 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 463 464 #if defined(CONFIG_CMD_KGDB) 465 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 466 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 467 #endif 468 469 /* 470 * Environment Configuration 471 */ 472 473 /* The mac addresses for all ethernet interface */ 474 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 475 #define CONFIG_HAS_ETH0 476 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 477 #define CONFIG_HAS_ETH1 478 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 479 #define CONFIG_HAS_ETH2 480 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 481 #define CONFIG_HAS_ETH3 482 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 483 #endif 484 485 #define CONFIG_IPADDR 192.168.1.253 486 487 #define CONFIG_HOSTNAME unknown 488 #define CONFIG_ROOTPATH /nfsroot 489 #define CONFIG_BOOTFILE your.uImage 490 491 #define CONFIG_SERVERIP 192.168.1.1 492 #define CONFIG_GATEWAYIP 192.168.1.1 493 #define CONFIG_NETMASK 255.255.255.0 494 495 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 496 497 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 498 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 499 500 #define CONFIG_BAUDRATE 115200 501 502 #define CONFIG_EXTRA_ENV_SETTINGS \ 503 "netdev=eth0\0" \ 504 "consoledev=ttyS0\0" \ 505 "ramdiskaddr=600000\0" \ 506 "ramdiskfile=your.ramdisk.u-boot\0" \ 507 "fdtaddr=400000\0" \ 508 "fdtfile=your.fdt.dtb\0" \ 509 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 510 "nfsroot=$serverip:$rootpath " \ 511 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 512 "console=$consoledev,$baudrate $othbootargs\0" \ 513 "ramargs=setenv bootargs root=/dev/ram rw " \ 514 "console=$consoledev,$baudrate $othbootargs\0" \ 515 516 517 #define CONFIG_NFSBOOTCOMMAND \ 518 "run nfsargs;" \ 519 "tftp $loadaddr $bootfile;" \ 520 "tftp $fdtaddr $fdtfile;" \ 521 "bootm $loadaddr - $fdtaddr" 522 523 524 #define CONFIG_RAMBOOTCOMMAND \ 525 "run ramargs;" \ 526 "tftp $ramdiskaddr $ramdiskfile;" \ 527 "tftp $loadaddr $bootfile;" \ 528 "bootm $loadaddr $ramdiskaddr" 529 530 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 531 532 #endif /* __CONFIG_H */ 533