xref: /openbmc/u-boot/include/configs/MPC8568MDS.h (revision ed09a554)
1 /*
2  * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * mpc8568mds board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 /* High Level Configuration Options */
14 #define CONFIG_BOOKE		1	/* BOOKE */
15 #define CONFIG_E500		1	/* BOOKE e500 family */
16 #define CONFIG_MPC8568		1	/* MPC8568 specific */
17 #define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
18 
19 #define	CONFIG_SYS_TEXT_BASE	0xfff80000
20 
21 #define CONFIG_SYS_SRIO
22 #define CONFIG_SRIO1			/* SRIO port 1 */
23 
24 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
25 #define CONFIG_PCI1		1	/* PCI controller */
26 #define CONFIG_PCIE1		1	/* PCIE controller */
27 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
28 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
29 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
30 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
31 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
32 #define CONFIG_QE			/* Enable QE */
33 #define CONFIG_ENV_OVERWRITE
34 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
35 
36 #ifndef __ASSEMBLY__
37 extern unsigned long get_clock_freq(void);
38 #endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
39 #define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
40 
41 /*
42  * These can be toggled for performance analysis, otherwise use default.
43  */
44 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
45 #define CONFIG_BTB				/* toggle branch predition */
46 
47 /*
48  * Only possible on E500 Version 2 or newer cores.
49  */
50 #define CONFIG_ENABLE_36BIT_PHYS	1
51 
52 
53 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
54 
55 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
56 #define CONFIG_SYS_MEMTEST_END		0x00400000
57 
58 #define CONFIG_SYS_CCSRBAR		0xe0000000
59 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
60 
61 /* DDR Setup */
62 #define CONFIG_SYS_FSL_DDR2
63 #undef CONFIG_FSL_DDR_INTERACTIVE
64 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
65 #define CONFIG_DDR_SPD
66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
67 
68 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
69 
70 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
71 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
72 
73 #define CONFIG_NUM_DDR_CONTROLLERS	1
74 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
75 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
76 
77 /* I2C addresses of SPD EEPROMs */
78 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
79 
80 /* Make sure required options are set */
81 #ifndef CONFIG_SPD_EEPROM
82 #error ("CONFIG_SPD_EEPROM is required")
83 #endif
84 
85 #undef CONFIG_CLOCKS_IN_MHZ
86 
87 /*
88  * Local Bus Definitions
89  */
90 
91 /*
92  * FLASH on the Local Bus
93  * Two banks, 8M each, using the CFI driver.
94  * Boot from BR0/OR0 bank at 0xff00_0000
95  * Alternate BR1/OR1 bank at 0xff80_0000
96  *
97  * BR0, BR1:
98  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
99  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
100  *    Port Size = 16 bits = BRx[19:20] = 10
101  *    Use GPCM = BRx[24:26] = 000
102  *    Valid = BRx[31] = 1
103  *
104  * 0    4    8    12   16   20   24   28
105  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
106  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
107  *
108  * OR0, OR1:
109  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
110  *    Reserved ORx[17:18] = 11, confusion here?
111  *    CSNT = ORx[20] = 1
112  *    ACS = half cycle delay = ORx[21:22] = 11
113  *    SCY = 6 = ORx[24:27] = 0110
114  *    TRLX = use relaxed timing = ORx[29] = 1
115  *    EAD = use external address latch delay = OR[31] = 1
116  *
117  * 0    4    8    12   16   20   24   28
118  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
119  */
120 #define CONFIG_SYS_BCSR_BASE		0xf8000000
121 
122 #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
123 
124 /*Chip select 0 - Flash*/
125 #define CONFIG_SYS_BR0_PRELIM		0xfe001001
126 #define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7
127 
128 /*Chip slelect 1 - BCSR*/
129 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
130 #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
131 
132 /*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
133 #define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
134 #define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
135 #undef	CONFIG_SYS_FLASH_CHECKSUM
136 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
137 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
138 
139 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
140 
141 #define CONFIG_FLASH_CFI_DRIVER
142 #define CONFIG_SYS_FLASH_CFI
143 #define CONFIG_SYS_FLASH_EMPTY_INFO
144 
145 
146 /*
147  * SDRAM on the LocalBus
148  */
149 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
150 #define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
151 
152 
153 /*Chip select 2 - SDRAM*/
154 #define CONFIG_SYS_BR2_PRELIM      0xf0001861
155 #define CONFIG_SYS_OR2_PRELIM		0xfc006901
156 
157 #define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
158 #define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
159 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
160 #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
161 
162 /*
163  * Common settings for all Local Bus SDRAM commands.
164  * At run time, either BSMA1516 (for CPU 1.1)
165  *                  or BSMA1617 (for CPU 1.0) (old)
166  * is OR'ed in too.
167  */
168 #define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
169 				| LSDMR_PRETOACT7	\
170 				| LSDMR_ACTTORW7	\
171 				| LSDMR_BL8		\
172 				| LSDMR_WRC4		\
173 				| LSDMR_CL3		\
174 				| LSDMR_RFEN		\
175 				)
176 
177 /*
178  * The bcsr registers are connected to CS3 on MDS.
179  * The new memory map places bcsr at 0xf8000000.
180  *
181  * For BR3, need:
182  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
183  *    port-size = 8-bits  = BR[19:20] = 01
184  *    no parity checking  = BR[21:22] = 00
185  *    GPMC for MSEL       = BR[24:26] = 000
186  *    Valid               = BR[31]    = 1
187  *
188  * 0    4    8    12   16   20   24   28
189  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
190  *
191  * For OR3, need:
192  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
193  *    disable buffer ctrl OR[19]    = 0
194  *    CSNT                OR[20]    = 1
195  *    ACS                 OR[21:22] = 11
196  *    XACS                OR[23]    = 1
197  *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
198  *    SETA                OR[28]    = 0
199  *    TRLX                OR[29]    = 1
200  *    EHTR                OR[30]    = 1
201  *    EAD extra time      OR[31]    = 1
202  *
203  * 0    4    8    12   16   20   24   28
204  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
205  */
206 #define CONFIG_SYS_BCSR (0xf8000000)
207 
208 /*Chip slelect 4 - PIB*/
209 #define CONFIG_SYS_BR4_PRELIM   0xf8008801
210 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
211 
212 /*Chip select 5 - PIB*/
213 #define CONFIG_SYS_BR5_PRELIM	 0xf8010801
214 #define CONFIG_SYS_OR5_PRELIM	 0xffff69f7
215 
216 #define CONFIG_SYS_INIT_RAM_LOCK	1
217 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
218 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
219 
220 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
221 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
222 
223 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
224 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
225 
226 /* Serial Port */
227 #define CONFIG_CONS_INDEX		1
228 #define CONFIG_SYS_NS16550
229 #define CONFIG_SYS_NS16550_SERIAL
230 #define CONFIG_SYS_NS16550_REG_SIZE    1
231 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
232 
233 #define CONFIG_SYS_BAUDRATE_TABLE  \
234 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
235 
236 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
237 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
238 
239 /* Use the HUSH parser*/
240 #define CONFIG_SYS_HUSH_PARSER
241 #ifdef  CONFIG_SYS_HUSH_PARSER
242 #endif
243 
244 /* pass open firmware flat tree */
245 #define CONFIG_OF_LIBFDT		1
246 #define CONFIG_OF_BOARD_SETUP		1
247 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
248 
249 /*
250  * I2C
251  */
252 #define CONFIG_SYS_I2C
253 #define CONFIG_SYS_I2C_FSL
254 #define CONFIG_SYS_FSL_I2C_SPEED	400000
255 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
256 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
257 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
258 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
259 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
260 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
261 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
262 
263 /*
264  * General PCI
265  * Memory Addresses are mapped 1-1. I/O is mapped from 0
266  */
267 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
268 #define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
269 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
270 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
271 #define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
272 #define CONFIG_SYS_PCI1_IO_BUS	0x00000000
273 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
274 #define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */
275 
276 #define CONFIG_SYS_PCIE1_NAME		"Slot"
277 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
278 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
279 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
280 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
281 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
282 #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
283 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
284 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
285 
286 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
287 #define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
288 #define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
289 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
290 
291 #ifdef CONFIG_QE
292 /*
293  * QE UEC ethernet configuration
294  */
295 #define CONFIG_UEC_ETH
296 #ifndef CONFIG_TSEC_ENET
297 #define CONFIG_ETHPRIME         "UEC0"
298 #endif
299 #define CONFIG_PHY_MODE_NEED_CHANGE
300 #define CONFIG_eTSEC_MDIO_BUS
301 
302 #ifdef CONFIG_eTSEC_MDIO_BUS
303 #define CONFIG_MIIM_ADDRESS	0xE0024520
304 #endif
305 
306 #define CONFIG_UEC_ETH1         /* GETH1 */
307 
308 #ifdef CONFIG_UEC_ETH1
309 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
310 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
311 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
312 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
313 #define CONFIG_SYS_UEC1_PHY_ADDR       7
314 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
315 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
316 #endif
317 
318 #define CONFIG_UEC_ETH2         /* GETH2 */
319 
320 #ifdef CONFIG_UEC_ETH2
321 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
322 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
323 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
324 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
325 #define CONFIG_SYS_UEC2_PHY_ADDR       1
326 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
327 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
328 #endif
329 #endif /* CONFIG_QE */
330 
331 #if defined(CONFIG_PCI)
332 
333 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
334 
335 #undef CONFIG_EEPRO100
336 #undef CONFIG_TULIP
337 
338 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
339 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
340 
341 #endif	/* CONFIG_PCI */
342 
343 #if defined(CONFIG_TSEC_ENET)
344 
345 #define CONFIG_MII		1	/* MII PHY management */
346 #define CONFIG_TSEC1	1
347 #define CONFIG_TSEC1_NAME	"eTSEC0"
348 #define CONFIG_TSEC2	1
349 #define CONFIG_TSEC2_NAME	"eTSEC1"
350 
351 #define TSEC1_PHY_ADDR		2
352 #define TSEC2_PHY_ADDR		3
353 
354 #define TSEC1_PHYIDX		0
355 #define TSEC2_PHYIDX		0
356 
357 #define TSEC1_FLAGS		TSEC_GIGABIT
358 #define TSEC2_FLAGS		TSEC_GIGABIT
359 
360 /* Options are: eTSEC[0-1] */
361 #define CONFIG_ETHPRIME		"eTSEC0"
362 
363 #endif	/* CONFIG_TSEC_ENET */
364 
365 /*
366  * Environment
367  */
368 #define CONFIG_ENV_IS_IN_FLASH	1
369 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
370 #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
371 #define CONFIG_ENV_SIZE		0x2000
372 
373 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
374 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
375 
376 
377 /*
378  * BOOTP options
379  */
380 #define CONFIG_BOOTP_BOOTFILESIZE
381 #define CONFIG_BOOTP_BOOTPATH
382 #define CONFIG_BOOTP_GATEWAY
383 #define CONFIG_BOOTP_HOSTNAME
384 
385 
386 /*
387  * Command line configuration.
388  */
389 #include <config_cmd_default.h>
390 
391 #define CONFIG_CMD_PING
392 #define CONFIG_CMD_I2C
393 #define CONFIG_CMD_MII
394 #define CONFIG_CMD_ELF
395 #define CONFIG_CMD_IRQ
396 #define CONFIG_CMD_SETEXPR
397 #define CONFIG_CMD_REGINFO
398 
399 #if defined(CONFIG_PCI)
400     #define CONFIG_CMD_PCI
401 #endif
402 
403 
404 #undef CONFIG_WATCHDOG			/* watchdog disabled */
405 
406 /*
407  * Miscellaneous configurable options
408  */
409 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
410 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
411 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
412 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
413 #if defined(CONFIG_CMD_KGDB)
414 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
415 #else
416 #define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size */
417 #endif
418 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
419 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
420 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
421 
422 /*
423  * For booting Linux, the board info and command line data
424  * have to be in the first 64 MB of memory, since this is
425  * the maximum mapped by the Linux kernel during initialization.
426  */
427 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
428 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
429 
430 #if defined(CONFIG_CMD_KGDB)
431 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
432 #endif
433 
434 /*
435  * Environment Configuration
436  */
437 
438 /* The mac addresses for all ethernet interface */
439 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
440 #define CONFIG_HAS_ETH0
441 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
442 #define CONFIG_HAS_ETH1
443 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
444 #define CONFIG_HAS_ETH2
445 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
446 #define CONFIG_HAS_ETH3
447 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
448 #endif
449 
450 #define CONFIG_IPADDR    192.168.1.253
451 
452 #define CONFIG_HOSTNAME  unknown
453 #define CONFIG_ROOTPATH  "/nfsroot"
454 #define CONFIG_BOOTFILE  "your.uImage"
455 
456 #define CONFIG_SERVERIP  192.168.1.1
457 #define CONFIG_GATEWAYIP 192.168.1.1
458 #define CONFIG_NETMASK   255.255.255.0
459 
460 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
461 
462 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
463 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
464 
465 #define CONFIG_BAUDRATE	115200
466 
467 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
468    "netdev=eth0\0"                                                      \
469    "consoledev=ttyS0\0"                                                 \
470    "ramdiskaddr=600000\0"                                               \
471    "ramdiskfile=your.ramdisk.u-boot\0"					\
472    "fdtaddr=400000\0"							\
473    "fdtfile=your.fdt.dtb\0"						\
474    "nfsargs=setenv bootargs root=/dev/nfs rw "				\
475       "nfsroot=$serverip:$rootpath "					\
476       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
477       "console=$consoledev,$baudrate $othbootargs\0"			\
478    "ramargs=setenv bootargs root=/dev/ram rw "				\
479       "console=$consoledev,$baudrate $othbootargs\0"			\
480 
481 
482 #define CONFIG_NFSBOOTCOMMAND	                                        \
483    "run nfsargs;"							\
484    "tftp $loadaddr $bootfile;"                                          \
485    "tftp $fdtaddr $fdtfile;"						\
486    "bootm $loadaddr - $fdtaddr"
487 
488 
489 #define CONFIG_RAMBOOTCOMMAND \
490    "run ramargs;"							\
491    "tftp $ramdiskaddr $ramdiskfile;"                                    \
492    "tftp $loadaddr $bootfile;"                                          \
493    "bootm $loadaddr $ramdiskaddr"
494 
495 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
496 
497 #endif	/* __CONFIG_H */
498