xref: /openbmc/u-boot/include/configs/MPC8568MDS.h (revision eb5ba3ae)
1  /*
2   * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
3   *
4   * SPDX-License-Identifier:	GPL-2.0+
5   */
6  
7  /*
8   * mpc8568mds board configuration file
9   */
10  #ifndef __CONFIG_H
11  #define __CONFIG_H
12  
13  #define	CONFIG_SYS_TEXT_BASE	0xfff80000
14  
15  #define CONFIG_SYS_SRIO
16  #define CONFIG_SRIO1			/* SRIO port 1 */
17  
18  #define CONFIG_PCI1		1	/* PCI controller */
19  #define CONFIG_PCIE1		1	/* PCIE controller */
20  #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
21  #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
22  #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
23  #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
24  #define CONFIG_TSEC_ENET		/* tsec ethernet support */
25  #define CONFIG_QE			/* Enable QE */
26  #define CONFIG_ENV_OVERWRITE
27  
28  #ifndef __ASSEMBLY__
29  extern unsigned long get_clock_freq(void);
30  #endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
31  #define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
32  
33  /*
34   * These can be toggled for performance analysis, otherwise use default.
35   */
36  #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
37  #define CONFIG_BTB				/* toggle branch predition */
38  
39  /*
40   * Only possible on E500 Version 2 or newer cores.
41   */
42  #define CONFIG_ENABLE_36BIT_PHYS	1
43  
44  #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
45  #define CONFIG_SYS_MEMTEST_END		0x00400000
46  
47  #define CONFIG_SYS_CCSRBAR		0xe0000000
48  #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
49  
50  /* DDR Setup */
51  #undef CONFIG_FSL_DDR_INTERACTIVE
52  #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
53  #define CONFIG_DDR_SPD
54  #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
55  
56  #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
57  
58  #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
59  #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
60  
61  #define CONFIG_DIMM_SLOTS_PER_CTLR	1
62  #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
63  
64  /* I2C addresses of SPD EEPROMs */
65  #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
66  
67  /* Make sure required options are set */
68  #ifndef CONFIG_SPD_EEPROM
69  #error ("CONFIG_SPD_EEPROM is required")
70  #endif
71  
72  #undef CONFIG_CLOCKS_IN_MHZ
73  
74  /*
75   * Local Bus Definitions
76   */
77  
78  /*
79   * FLASH on the Local Bus
80   * Two banks, 8M each, using the CFI driver.
81   * Boot from BR0/OR0 bank at 0xff00_0000
82   * Alternate BR1/OR1 bank at 0xff80_0000
83   *
84   * BR0, BR1:
85   *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
86   *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
87   *    Port Size = 16 bits = BRx[19:20] = 10
88   *    Use GPCM = BRx[24:26] = 000
89   *    Valid = BRx[31] = 1
90   *
91   * 0    4    8    12   16   20   24   28
92   * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
93   * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
94   *
95   * OR0, OR1:
96   *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
97   *    Reserved ORx[17:18] = 11, confusion here?
98   *    CSNT = ORx[20] = 1
99   *    ACS = half cycle delay = ORx[21:22] = 11
100   *    SCY = 6 = ORx[24:27] = 0110
101   *    TRLX = use relaxed timing = ORx[29] = 1
102   *    EAD = use external address latch delay = OR[31] = 1
103   *
104   * 0    4    8    12   16   20   24   28
105   * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
106   */
107  #define CONFIG_SYS_BCSR_BASE		0xf8000000
108  
109  #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
110  
111  /*Chip select 0 - Flash*/
112  #define CONFIG_SYS_BR0_PRELIM		0xfe001001
113  #define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7
114  
115  /*Chip slelect 1 - BCSR*/
116  #define CONFIG_SYS_BR1_PRELIM		0xf8000801
117  #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
118  
119  /*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
120  #define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
121  #define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
122  #undef	CONFIG_SYS_FLASH_CHECKSUM
123  #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
124  #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
125  
126  #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
127  
128  #define CONFIG_FLASH_CFI_DRIVER
129  #define CONFIG_SYS_FLASH_CFI
130  #define CONFIG_SYS_FLASH_EMPTY_INFO
131  
132  /*
133   * SDRAM on the LocalBus
134   */
135  #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
136  #define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
137  
138  /*Chip select 2 - SDRAM*/
139  #define CONFIG_SYS_BR2_PRELIM      0xf0001861
140  #define CONFIG_SYS_OR2_PRELIM		0xfc006901
141  
142  #define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
143  #define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
144  #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
145  #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
146  
147  /*
148   * Common settings for all Local Bus SDRAM commands.
149   * At run time, either BSMA1516 (for CPU 1.1)
150   *                  or BSMA1617 (for CPU 1.0) (old)
151   * is OR'ed in too.
152   */
153  #define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
154  				| LSDMR_PRETOACT7	\
155  				| LSDMR_ACTTORW7	\
156  				| LSDMR_BL8		\
157  				| LSDMR_WRC4		\
158  				| LSDMR_CL3		\
159  				| LSDMR_RFEN		\
160  				)
161  
162  /*
163   * The bcsr registers are connected to CS3 on MDS.
164   * The new memory map places bcsr at 0xf8000000.
165   *
166   * For BR3, need:
167   *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
168   *    port-size = 8-bits  = BR[19:20] = 01
169   *    no parity checking  = BR[21:22] = 00
170   *    GPMC for MSEL       = BR[24:26] = 000
171   *    Valid               = BR[31]    = 1
172   *
173   * 0    4    8    12   16   20   24   28
174   * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
175   *
176   * For OR3, need:
177   *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
178   *    disable buffer ctrl OR[19]    = 0
179   *    CSNT                OR[20]    = 1
180   *    ACS                 OR[21:22] = 11
181   *    XACS                OR[23]    = 1
182   *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
183   *    SETA                OR[28]    = 0
184   *    TRLX                OR[29]    = 1
185   *    EHTR                OR[30]    = 1
186   *    EAD extra time      OR[31]    = 1
187   *
188   * 0    4    8    12   16   20   24   28
189   * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
190   */
191  #define CONFIG_SYS_BCSR (0xf8000000)
192  
193  /*Chip slelect 4 - PIB*/
194  #define CONFIG_SYS_BR4_PRELIM   0xf8008801
195  #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
196  
197  /*Chip select 5 - PIB*/
198  #define CONFIG_SYS_BR5_PRELIM	 0xf8010801
199  #define CONFIG_SYS_OR5_PRELIM	 0xffff69f7
200  
201  #define CONFIG_SYS_INIT_RAM_LOCK	1
202  #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
203  #define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
204  
205  #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
206  #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
207  
208  #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
209  #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
210  
211  /* Serial Port */
212  #define CONFIG_CONS_INDEX		1
213  #define CONFIG_SYS_NS16550_SERIAL
214  #define CONFIG_SYS_NS16550_REG_SIZE    1
215  #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
216  
217  #define CONFIG_SYS_BAUDRATE_TABLE  \
218  	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
219  
220  #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
221  #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
222  
223  /*
224   * I2C
225   */
226  #define CONFIG_SYS_I2C
227  #define CONFIG_SYS_I2C_FSL
228  #define CONFIG_SYS_FSL_I2C_SPEED	400000
229  #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
230  #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
231  #define CONFIG_SYS_FSL_I2C2_SPEED	400000
232  #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
233  #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
234  #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
235  #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
236  
237  /*
238   * General PCI
239   * Memory Addresses are mapped 1-1. I/O is mapped from 0
240   */
241  #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
242  #define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
243  #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
244  #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
245  #define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
246  #define CONFIG_SYS_PCI1_IO_BUS	0x00000000
247  #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
248  #define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */
249  
250  #define CONFIG_SYS_PCIE1_NAME		"Slot"
251  #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
252  #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
253  #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
254  #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
255  #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
256  #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
257  #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
258  #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
259  
260  #define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
261  #define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
262  #define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
263  #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
264  
265  #ifdef CONFIG_QE
266  /*
267   * QE UEC ethernet configuration
268   */
269  #define CONFIG_UEC_ETH
270  #ifndef CONFIG_TSEC_ENET
271  #define CONFIG_ETHPRIME         "UEC0"
272  #endif
273  #define CONFIG_PHY_MODE_NEED_CHANGE
274  #define CONFIG_eTSEC_MDIO_BUS
275  
276  #ifdef CONFIG_eTSEC_MDIO_BUS
277  #define CONFIG_MIIM_ADDRESS	0xE0024520
278  #endif
279  
280  #define CONFIG_UEC_ETH1         /* GETH1 */
281  
282  #ifdef CONFIG_UEC_ETH1
283  #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
284  #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
285  #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
286  #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
287  #define CONFIG_SYS_UEC1_PHY_ADDR       7
288  #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
289  #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
290  #endif
291  
292  #define CONFIG_UEC_ETH2         /* GETH2 */
293  
294  #ifdef CONFIG_UEC_ETH2
295  #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
296  #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
297  #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
298  #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
299  #define CONFIG_SYS_UEC2_PHY_ADDR       1
300  #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
301  #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
302  #endif
303  #endif /* CONFIG_QE */
304  
305  #if defined(CONFIG_PCI)
306  #undef CONFIG_EEPRO100
307  #undef CONFIG_TULIP
308  
309  #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
310  #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
311  
312  #endif	/* CONFIG_PCI */
313  
314  #if defined(CONFIG_TSEC_ENET)
315  
316  #define CONFIG_MII		1	/* MII PHY management */
317  #define CONFIG_TSEC1	1
318  #define CONFIG_TSEC1_NAME	"eTSEC0"
319  #define CONFIG_TSEC2	1
320  #define CONFIG_TSEC2_NAME	"eTSEC1"
321  
322  #define TSEC1_PHY_ADDR		2
323  #define TSEC2_PHY_ADDR		3
324  
325  #define TSEC1_PHYIDX		0
326  #define TSEC2_PHYIDX		0
327  
328  #define TSEC1_FLAGS		TSEC_GIGABIT
329  #define TSEC2_FLAGS		TSEC_GIGABIT
330  
331  /* Options are: eTSEC[0-1] */
332  #define CONFIG_ETHPRIME		"eTSEC0"
333  
334  #endif	/* CONFIG_TSEC_ENET */
335  
336  /*
337   * Environment
338   */
339  #define CONFIG_ENV_IS_IN_FLASH	1
340  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
341  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
342  #define CONFIG_ENV_SIZE		0x2000
343  
344  #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
345  #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
346  
347  /*
348   * BOOTP options
349   */
350  #define CONFIG_BOOTP_BOOTFILESIZE
351  #define CONFIG_BOOTP_BOOTPATH
352  #define CONFIG_BOOTP_GATEWAY
353  #define CONFIG_BOOTP_HOSTNAME
354  
355  /*
356   * Command line configuration.
357   */
358  #define CONFIG_CMD_IRQ
359  #define CONFIG_CMD_REGINFO
360  
361  #if defined(CONFIG_PCI)
362      #define CONFIG_CMD_PCI
363  #endif
364  
365  #undef CONFIG_WATCHDOG			/* watchdog disabled */
366  
367  /*
368   * Miscellaneous configurable options
369   */
370  #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
371  #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
372  #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
373  #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
374  #if defined(CONFIG_CMD_KGDB)
375  #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
376  #else
377  #define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size */
378  #endif
379  #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
380  #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
381  #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
382  
383  /*
384   * For booting Linux, the board info and command line data
385   * have to be in the first 64 MB of memory, since this is
386   * the maximum mapped by the Linux kernel during initialization.
387   */
388  #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
389  #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
390  
391  #if defined(CONFIG_CMD_KGDB)
392  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
393  #endif
394  
395  /*
396   * Environment Configuration
397   */
398  
399  /* The mac addresses for all ethernet interface */
400  #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
401  #define CONFIG_HAS_ETH0
402  #define CONFIG_HAS_ETH1
403  #define CONFIG_HAS_ETH2
404  #define CONFIG_HAS_ETH3
405  #endif
406  
407  #define CONFIG_IPADDR    192.168.1.253
408  
409  #define CONFIG_HOSTNAME  unknown
410  #define CONFIG_ROOTPATH  "/nfsroot"
411  #define CONFIG_BOOTFILE  "your.uImage"
412  
413  #define CONFIG_SERVERIP  192.168.1.1
414  #define CONFIG_GATEWAYIP 192.168.1.1
415  #define CONFIG_NETMASK   255.255.255.0
416  
417  #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
418  
419  #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
420  
421  #define	CONFIG_EXTRA_ENV_SETTINGS				        \
422     "netdev=eth0\0"                                                      \
423     "consoledev=ttyS0\0"                                                 \
424     "ramdiskaddr=600000\0"                                               \
425     "ramdiskfile=your.ramdisk.u-boot\0"					\
426     "fdtaddr=400000\0"							\
427     "fdtfile=your.fdt.dtb\0"						\
428     "nfsargs=setenv bootargs root=/dev/nfs rw "				\
429        "nfsroot=$serverip:$rootpath "					\
430        "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
431        "console=$consoledev,$baudrate $othbootargs\0"			\
432     "ramargs=setenv bootargs root=/dev/ram rw "				\
433        "console=$consoledev,$baudrate $othbootargs\0"			\
434  
435  #define CONFIG_NFSBOOTCOMMAND	                                        \
436     "run nfsargs;"							\
437     "tftp $loadaddr $bootfile;"                                          \
438     "tftp $fdtaddr $fdtfile;"						\
439     "bootm $loadaddr - $fdtaddr"
440  
441  #define CONFIG_RAMBOOTCOMMAND \
442     "run ramargs;"							\
443     "tftp $ramdiskaddr $ramdiskfile;"                                    \
444     "tftp $loadaddr $bootfile;"                                          \
445     "bootm $loadaddr $ramdiskaddr"
446  
447  #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
448  
449  #endif	/* __CONFIG_H */
450