1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8568mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 17 #define CONFIG_SYS_TEXT_BASE 0xfff80000 18 19 #define CONFIG_SYS_SRIO 20 #define CONFIG_SRIO1 /* SRIO port 1 */ 21 22 #define CONFIG_PCI1 1 /* PCI controller */ 23 #define CONFIG_PCIE1 1 /* PCIE controller */ 24 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 25 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 26 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 27 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 28 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 29 #define CONFIG_QE /* Enable QE */ 30 #define CONFIG_ENV_OVERWRITE 31 32 #ifndef __ASSEMBLY__ 33 extern unsigned long get_clock_freq(void); 34 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 35 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 36 37 /* 38 * These can be toggled for performance analysis, otherwise use default. 39 */ 40 #define CONFIG_L2_CACHE /* toggle L2 cache */ 41 #define CONFIG_BTB /* toggle branch predition */ 42 43 /* 44 * Only possible on E500 Version 2 or newer cores. 45 */ 46 #define CONFIG_ENABLE_36BIT_PHYS 1 47 48 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 49 50 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 51 #define CONFIG_SYS_MEMTEST_END 0x00400000 52 53 #define CONFIG_SYS_CCSRBAR 0xe0000000 54 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 55 56 /* DDR Setup */ 57 #define CONFIG_SYS_FSL_DDR2 58 #undef CONFIG_FSL_DDR_INTERACTIVE 59 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 60 #define CONFIG_DDR_SPD 61 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 62 63 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 64 65 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 67 68 #define CONFIG_NUM_DDR_CONTROLLERS 1 69 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 70 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 71 72 /* I2C addresses of SPD EEPROMs */ 73 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 74 75 /* Make sure required options are set */ 76 #ifndef CONFIG_SPD_EEPROM 77 #error ("CONFIG_SPD_EEPROM is required") 78 #endif 79 80 #undef CONFIG_CLOCKS_IN_MHZ 81 82 /* 83 * Local Bus Definitions 84 */ 85 86 /* 87 * FLASH on the Local Bus 88 * Two banks, 8M each, using the CFI driver. 89 * Boot from BR0/OR0 bank at 0xff00_0000 90 * Alternate BR1/OR1 bank at 0xff80_0000 91 * 92 * BR0, BR1: 93 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 94 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 95 * Port Size = 16 bits = BRx[19:20] = 10 96 * Use GPCM = BRx[24:26] = 000 97 * Valid = BRx[31] = 1 98 * 99 * 0 4 8 12 16 20 24 28 100 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 101 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 102 * 103 * OR0, OR1: 104 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 105 * Reserved ORx[17:18] = 11, confusion here? 106 * CSNT = ORx[20] = 1 107 * ACS = half cycle delay = ORx[21:22] = 11 108 * SCY = 6 = ORx[24:27] = 0110 109 * TRLX = use relaxed timing = ORx[29] = 1 110 * EAD = use external address latch delay = OR[31] = 1 111 * 112 * 0 4 8 12 16 20 24 28 113 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 114 */ 115 #define CONFIG_SYS_BCSR_BASE 0xf8000000 116 117 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 118 119 /*Chip select 0 - Flash*/ 120 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 121 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 122 123 /*Chip slelect 1 - BCSR*/ 124 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 125 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 126 127 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 128 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 129 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 130 #undef CONFIG_SYS_FLASH_CHECKSUM 131 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 132 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 133 134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 135 136 #define CONFIG_FLASH_CFI_DRIVER 137 #define CONFIG_SYS_FLASH_CFI 138 #define CONFIG_SYS_FLASH_EMPTY_INFO 139 140 /* 141 * SDRAM on the LocalBus 142 */ 143 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 144 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 145 146 /*Chip select 2 - SDRAM*/ 147 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 148 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 149 150 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 151 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 152 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 153 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 154 155 /* 156 * Common settings for all Local Bus SDRAM commands. 157 * At run time, either BSMA1516 (for CPU 1.1) 158 * or BSMA1617 (for CPU 1.0) (old) 159 * is OR'ed in too. 160 */ 161 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 162 | LSDMR_PRETOACT7 \ 163 | LSDMR_ACTTORW7 \ 164 | LSDMR_BL8 \ 165 | LSDMR_WRC4 \ 166 | LSDMR_CL3 \ 167 | LSDMR_RFEN \ 168 ) 169 170 /* 171 * The bcsr registers are connected to CS3 on MDS. 172 * The new memory map places bcsr at 0xf8000000. 173 * 174 * For BR3, need: 175 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 176 * port-size = 8-bits = BR[19:20] = 01 177 * no parity checking = BR[21:22] = 00 178 * GPMC for MSEL = BR[24:26] = 000 179 * Valid = BR[31] = 1 180 * 181 * 0 4 8 12 16 20 24 28 182 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 183 * 184 * For OR3, need: 185 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 186 * disable buffer ctrl OR[19] = 0 187 * CSNT OR[20] = 1 188 * ACS OR[21:22] = 11 189 * XACS OR[23] = 1 190 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 191 * SETA OR[28] = 0 192 * TRLX OR[29] = 1 193 * EHTR OR[30] = 1 194 * EAD extra time OR[31] = 1 195 * 196 * 0 4 8 12 16 20 24 28 197 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 198 */ 199 #define CONFIG_SYS_BCSR (0xf8000000) 200 201 /*Chip slelect 4 - PIB*/ 202 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 203 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 204 205 /*Chip select 5 - PIB*/ 206 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 207 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 208 209 #define CONFIG_SYS_INIT_RAM_LOCK 1 210 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 211 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 212 213 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 214 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 215 216 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 217 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 218 219 /* Serial Port */ 220 #define CONFIG_CONS_INDEX 1 221 #define CONFIG_SYS_NS16550_SERIAL 222 #define CONFIG_SYS_NS16550_REG_SIZE 1 223 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 224 225 #define CONFIG_SYS_BAUDRATE_TABLE \ 226 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 227 228 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 229 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 230 231 /* 232 * I2C 233 */ 234 #define CONFIG_SYS_I2C 235 #define CONFIG_SYS_I2C_FSL 236 #define CONFIG_SYS_FSL_I2C_SPEED 400000 237 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 238 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 239 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 240 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 241 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 242 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 243 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 244 245 /* 246 * General PCI 247 * Memory Addresses are mapped 1-1. I/O is mapped from 0 248 */ 249 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 250 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 251 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 252 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 253 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 254 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 255 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 256 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 257 258 #define CONFIG_SYS_PCIE1_NAME "Slot" 259 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 260 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 261 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 262 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 263 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 264 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 265 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 266 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 267 268 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 269 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 270 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 271 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 272 273 #ifdef CONFIG_QE 274 /* 275 * QE UEC ethernet configuration 276 */ 277 #define CONFIG_UEC_ETH 278 #ifndef CONFIG_TSEC_ENET 279 #define CONFIG_ETHPRIME "UEC0" 280 #endif 281 #define CONFIG_PHY_MODE_NEED_CHANGE 282 #define CONFIG_eTSEC_MDIO_BUS 283 284 #ifdef CONFIG_eTSEC_MDIO_BUS 285 #define CONFIG_MIIM_ADDRESS 0xE0024520 286 #endif 287 288 #define CONFIG_UEC_ETH1 /* GETH1 */ 289 290 #ifdef CONFIG_UEC_ETH1 291 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 292 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 293 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 294 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 295 #define CONFIG_SYS_UEC1_PHY_ADDR 7 296 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 297 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 298 #endif 299 300 #define CONFIG_UEC_ETH2 /* GETH2 */ 301 302 #ifdef CONFIG_UEC_ETH2 303 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 304 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 305 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 306 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 307 #define CONFIG_SYS_UEC2_PHY_ADDR 1 308 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 309 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 310 #endif 311 #endif /* CONFIG_QE */ 312 313 #if defined(CONFIG_PCI) 314 #undef CONFIG_EEPRO100 315 #undef CONFIG_TULIP 316 317 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 318 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 319 320 #endif /* CONFIG_PCI */ 321 322 #if defined(CONFIG_TSEC_ENET) 323 324 #define CONFIG_MII 1 /* MII PHY management */ 325 #define CONFIG_TSEC1 1 326 #define CONFIG_TSEC1_NAME "eTSEC0" 327 #define CONFIG_TSEC2 1 328 #define CONFIG_TSEC2_NAME "eTSEC1" 329 330 #define TSEC1_PHY_ADDR 2 331 #define TSEC2_PHY_ADDR 3 332 333 #define TSEC1_PHYIDX 0 334 #define TSEC2_PHYIDX 0 335 336 #define TSEC1_FLAGS TSEC_GIGABIT 337 #define TSEC2_FLAGS TSEC_GIGABIT 338 339 /* Options are: eTSEC[0-1] */ 340 #define CONFIG_ETHPRIME "eTSEC0" 341 342 #endif /* CONFIG_TSEC_ENET */ 343 344 /* 345 * Environment 346 */ 347 #define CONFIG_ENV_IS_IN_FLASH 1 348 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 349 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 350 #define CONFIG_ENV_SIZE 0x2000 351 352 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 353 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 354 355 /* 356 * BOOTP options 357 */ 358 #define CONFIG_BOOTP_BOOTFILESIZE 359 #define CONFIG_BOOTP_BOOTPATH 360 #define CONFIG_BOOTP_GATEWAY 361 #define CONFIG_BOOTP_HOSTNAME 362 363 /* 364 * Command line configuration. 365 */ 366 #define CONFIG_CMD_IRQ 367 #define CONFIG_CMD_REGINFO 368 369 #if defined(CONFIG_PCI) 370 #define CONFIG_CMD_PCI 371 #endif 372 373 #undef CONFIG_WATCHDOG /* watchdog disabled */ 374 375 /* 376 * Miscellaneous configurable options 377 */ 378 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 379 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 380 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 381 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 382 #if defined(CONFIG_CMD_KGDB) 383 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 384 #else 385 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 386 #endif 387 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 388 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 389 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 390 391 /* 392 * For booting Linux, the board info and command line data 393 * have to be in the first 64 MB of memory, since this is 394 * the maximum mapped by the Linux kernel during initialization. 395 */ 396 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 397 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 398 399 #if defined(CONFIG_CMD_KGDB) 400 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 401 #endif 402 403 /* 404 * Environment Configuration 405 */ 406 407 /* The mac addresses for all ethernet interface */ 408 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 409 #define CONFIG_HAS_ETH0 410 #define CONFIG_HAS_ETH1 411 #define CONFIG_HAS_ETH2 412 #define CONFIG_HAS_ETH3 413 #endif 414 415 #define CONFIG_IPADDR 192.168.1.253 416 417 #define CONFIG_HOSTNAME unknown 418 #define CONFIG_ROOTPATH "/nfsroot" 419 #define CONFIG_BOOTFILE "your.uImage" 420 421 #define CONFIG_SERVERIP 192.168.1.1 422 #define CONFIG_GATEWAYIP 192.168.1.1 423 #define CONFIG_NETMASK 255.255.255.0 424 425 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 426 427 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 428 429 #define CONFIG_BAUDRATE 115200 430 431 #define CONFIG_EXTRA_ENV_SETTINGS \ 432 "netdev=eth0\0" \ 433 "consoledev=ttyS0\0" \ 434 "ramdiskaddr=600000\0" \ 435 "ramdiskfile=your.ramdisk.u-boot\0" \ 436 "fdtaddr=400000\0" \ 437 "fdtfile=your.fdt.dtb\0" \ 438 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 439 "nfsroot=$serverip:$rootpath " \ 440 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 441 "console=$consoledev,$baudrate $othbootargs\0" \ 442 "ramargs=setenv bootargs root=/dev/ram rw " \ 443 "console=$consoledev,$baudrate $othbootargs\0" \ 444 445 #define CONFIG_NFSBOOTCOMMAND \ 446 "run nfsargs;" \ 447 "tftp $loadaddr $bootfile;" \ 448 "tftp $fdtaddr $fdtfile;" \ 449 "bootm $loadaddr - $fdtaddr" 450 451 #define CONFIG_RAMBOOTCOMMAND \ 452 "run ramargs;" \ 453 "tftp $ramdiskaddr $ramdiskfile;" \ 454 "tftp $loadaddr $bootfile;" \ 455 "bootm $loadaddr $ramdiskaddr" 456 457 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 458 459 #endif /* __CONFIG_H */ 460