1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8568mds board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_SRIO 13 #define CONFIG_SRIO1 /* SRIO port 1 */ 14 15 #define CONFIG_PCI1 1 /* PCI controller */ 16 #define CONFIG_PCIE1 1 /* PCIE controller */ 17 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 18 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 19 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 21 #define CONFIG_QE /* Enable QE */ 22 #define CONFIG_ENV_OVERWRITE 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_clock_freq(void); 26 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 27 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 28 29 /* 30 * These can be toggled for performance analysis, otherwise use default. 31 */ 32 #define CONFIG_L2_CACHE /* toggle L2 cache */ 33 #define CONFIG_BTB /* toggle branch predition */ 34 35 /* 36 * Only possible on E500 Version 2 or newer cores. 37 */ 38 #define CONFIG_ENABLE_36BIT_PHYS 1 39 40 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 41 #define CONFIG_SYS_MEMTEST_END 0x00400000 42 43 #define CONFIG_SYS_CCSRBAR 0xe0000000 44 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 45 46 /* DDR Setup */ 47 #undef CONFIG_FSL_DDR_INTERACTIVE 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 49 #define CONFIG_DDR_SPD 50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 51 52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 53 54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 56 57 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 58 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 59 60 /* I2C addresses of SPD EEPROMs */ 61 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 62 63 /* Make sure required options are set */ 64 #ifndef CONFIG_SPD_EEPROM 65 #error ("CONFIG_SPD_EEPROM is required") 66 #endif 67 68 #undef CONFIG_CLOCKS_IN_MHZ 69 70 /* 71 * Local Bus Definitions 72 */ 73 74 /* 75 * FLASH on the Local Bus 76 * Two banks, 8M each, using the CFI driver. 77 * Boot from BR0/OR0 bank at 0xff00_0000 78 * Alternate BR1/OR1 bank at 0xff80_0000 79 * 80 * BR0, BR1: 81 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 82 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 83 * Port Size = 16 bits = BRx[19:20] = 10 84 * Use GPCM = BRx[24:26] = 000 85 * Valid = BRx[31] = 1 86 * 87 * 0 4 8 12 16 20 24 28 88 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 89 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 90 * 91 * OR0, OR1: 92 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 93 * Reserved ORx[17:18] = 11, confusion here? 94 * CSNT = ORx[20] = 1 95 * ACS = half cycle delay = ORx[21:22] = 11 96 * SCY = 6 = ORx[24:27] = 0110 97 * TRLX = use relaxed timing = ORx[29] = 1 98 * EAD = use external address latch delay = OR[31] = 1 99 * 100 * 0 4 8 12 16 20 24 28 101 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 102 */ 103 #define CONFIG_SYS_BCSR_BASE 0xf8000000 104 105 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 106 107 /*Chip select 0 - Flash*/ 108 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 109 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 110 111 /*Chip slelect 1 - BCSR*/ 112 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 113 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 114 115 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 116 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 117 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 118 #undef CONFIG_SYS_FLASH_CHECKSUM 119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 121 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 123 124 #define CONFIG_SYS_FLASH_EMPTY_INFO 125 126 /* 127 * SDRAM on the LocalBus 128 */ 129 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 130 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 131 132 /*Chip select 2 - SDRAM*/ 133 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 134 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 135 136 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 137 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 138 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 139 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 140 141 /* 142 * Common settings for all Local Bus SDRAM commands. 143 * At run time, either BSMA1516 (for CPU 1.1) 144 * or BSMA1617 (for CPU 1.0) (old) 145 * is OR'ed in too. 146 */ 147 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 148 | LSDMR_PRETOACT7 \ 149 | LSDMR_ACTTORW7 \ 150 | LSDMR_BL8 \ 151 | LSDMR_WRC4 \ 152 | LSDMR_CL3 \ 153 | LSDMR_RFEN \ 154 ) 155 156 /* 157 * The bcsr registers are connected to CS3 on MDS. 158 * The new memory map places bcsr at 0xf8000000. 159 * 160 * For BR3, need: 161 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 162 * port-size = 8-bits = BR[19:20] = 01 163 * no parity checking = BR[21:22] = 00 164 * GPMC for MSEL = BR[24:26] = 000 165 * Valid = BR[31] = 1 166 * 167 * 0 4 8 12 16 20 24 28 168 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 169 * 170 * For OR3, need: 171 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 172 * disable buffer ctrl OR[19] = 0 173 * CSNT OR[20] = 1 174 * ACS OR[21:22] = 11 175 * XACS OR[23] = 1 176 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 177 * SETA OR[28] = 0 178 * TRLX OR[29] = 1 179 * EHTR OR[30] = 1 180 * EAD extra time OR[31] = 1 181 * 182 * 0 4 8 12 16 20 24 28 183 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 184 */ 185 #define CONFIG_SYS_BCSR (0xf8000000) 186 187 /*Chip slelect 4 - PIB*/ 188 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 189 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 190 191 /*Chip select 5 - PIB*/ 192 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 193 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 194 195 #define CONFIG_SYS_INIT_RAM_LOCK 1 196 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 197 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 198 199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 201 202 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 203 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 204 205 /* Serial Port */ 206 #define CONFIG_SYS_NS16550_SERIAL 207 #define CONFIG_SYS_NS16550_REG_SIZE 1 208 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 209 210 #define CONFIG_SYS_BAUDRATE_TABLE \ 211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 212 213 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 214 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 215 216 /* 217 * I2C 218 */ 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_FSL 221 #define CONFIG_SYS_FSL_I2C_SPEED 400000 222 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 223 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 224 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 225 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 226 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 227 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 228 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 229 230 /* 231 * General PCI 232 * Memory Addresses are mapped 1-1. I/O is mapped from 0 233 */ 234 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 235 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 236 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 237 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 238 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 239 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 241 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 242 243 #define CONFIG_SYS_PCIE1_NAME "Slot" 244 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 245 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 247 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 248 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 249 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 251 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 252 253 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 254 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 255 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 256 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 257 258 #ifdef CONFIG_QE 259 /* 260 * QE UEC ethernet configuration 261 */ 262 #define CONFIG_UEC_ETH 263 #ifndef CONFIG_TSEC_ENET 264 #define CONFIG_ETHPRIME "UEC0" 265 #endif 266 #define CONFIG_PHY_MODE_NEED_CHANGE 267 #define CONFIG_eTSEC_MDIO_BUS 268 269 #ifdef CONFIG_eTSEC_MDIO_BUS 270 #define CONFIG_MIIM_ADDRESS 0xE0024520 271 #endif 272 273 #define CONFIG_UEC_ETH1 /* GETH1 */ 274 275 #ifdef CONFIG_UEC_ETH1 276 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 277 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 278 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 279 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 280 #define CONFIG_SYS_UEC1_PHY_ADDR 7 281 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 282 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 283 #endif 284 285 #define CONFIG_UEC_ETH2 /* GETH2 */ 286 287 #ifdef CONFIG_UEC_ETH2 288 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 289 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 290 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 291 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 292 #define CONFIG_SYS_UEC2_PHY_ADDR 1 293 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 294 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 295 #endif 296 #endif /* CONFIG_QE */ 297 298 #if defined(CONFIG_PCI) 299 #undef CONFIG_EEPRO100 300 #undef CONFIG_TULIP 301 302 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 303 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 304 305 #endif /* CONFIG_PCI */ 306 307 #if defined(CONFIG_TSEC_ENET) 308 309 #define CONFIG_TSEC1 1 310 #define CONFIG_TSEC1_NAME "eTSEC0" 311 #define CONFIG_TSEC2 1 312 #define CONFIG_TSEC2_NAME "eTSEC1" 313 314 #define TSEC1_PHY_ADDR 2 315 #define TSEC2_PHY_ADDR 3 316 317 #define TSEC1_PHYIDX 0 318 #define TSEC2_PHYIDX 0 319 320 #define TSEC1_FLAGS TSEC_GIGABIT 321 #define TSEC2_FLAGS TSEC_GIGABIT 322 323 /* Options are: eTSEC[0-1] */ 324 #define CONFIG_ETHPRIME "eTSEC0" 325 326 #endif /* CONFIG_TSEC_ENET */ 327 328 /* 329 * Environment 330 */ 331 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 332 #define CONFIG_ENV_SIZE 0x2000 333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 334 335 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 336 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 337 338 /* 339 * BOOTP options 340 */ 341 #define CONFIG_BOOTP_BOOTFILESIZE 342 343 #undef CONFIG_WATCHDOG /* watchdog disabled */ 344 345 /* 346 * Miscellaneous configurable options 347 */ 348 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 349 350 /* 351 * For booting Linux, the board info and command line data 352 * have to be in the first 64 MB of memory, since this is 353 * the maximum mapped by the Linux kernel during initialization. 354 */ 355 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 356 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 357 358 #if defined(CONFIG_CMD_KGDB) 359 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 360 #endif 361 362 /* 363 * Environment Configuration 364 */ 365 366 /* The mac addresses for all ethernet interface */ 367 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 368 #define CONFIG_HAS_ETH0 369 #define CONFIG_HAS_ETH1 370 #define CONFIG_HAS_ETH2 371 #define CONFIG_HAS_ETH3 372 #endif 373 374 #define CONFIG_IPADDR 192.168.1.253 375 376 #define CONFIG_HOSTNAME "unknown" 377 #define CONFIG_ROOTPATH "/nfsroot" 378 #define CONFIG_BOOTFILE "your.uImage" 379 380 #define CONFIG_SERVERIP 192.168.1.1 381 #define CONFIG_GATEWAYIP 192.168.1.1 382 #define CONFIG_NETMASK 255.255.255.0 383 384 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 385 386 #define CONFIG_EXTRA_ENV_SETTINGS \ 387 "netdev=eth0\0" \ 388 "consoledev=ttyS0\0" \ 389 "ramdiskaddr=600000\0" \ 390 "ramdiskfile=your.ramdisk.u-boot\0" \ 391 "fdtaddr=400000\0" \ 392 "fdtfile=your.fdt.dtb\0" \ 393 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 394 "nfsroot=$serverip:$rootpath " \ 395 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 396 "console=$consoledev,$baudrate $othbootargs\0" \ 397 "ramargs=setenv bootargs root=/dev/ram rw " \ 398 "console=$consoledev,$baudrate $othbootargs\0" \ 399 400 #define CONFIG_NFSBOOTCOMMAND \ 401 "run nfsargs;" \ 402 "tftp $loadaddr $bootfile;" \ 403 "tftp $fdtaddr $fdtfile;" \ 404 "bootm $loadaddr - $fdtaddr" 405 406 #define CONFIG_RAMBOOTCOMMAND \ 407 "run ramargs;" \ 408 "tftp $ramdiskaddr $ramdiskfile;" \ 409 "tftp $loadaddr $bootfile;" \ 410 "bootm $loadaddr $ramdiskaddr" 411 412 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 413 414 #endif /* __CONFIG_H */ 415