1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_SYS_TEXT_BASE 0xfff80000 37 38 #define CONFIG_SYS_SRIO 39 #define CONFIG_SRIO1 /* SRIO port 1 */ 40 41 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 42 #define CONFIG_PCI1 1 /* PCI controller */ 43 #define CONFIG_PCIE1 1 /* PCIE controller */ 44 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 45 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_QE /* Enable QE */ 49 #define CONFIG_ENV_OVERWRITE 50 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 51 52 #ifndef __ASSEMBLY__ 53 extern unsigned long get_clock_freq(void); 54 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 55 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 56 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CONFIG_L2_CACHE /* toggle L2 cache */ 61 #define CONFIG_BTB /* toggle branch predition */ 62 63 /* 64 * Only possible on E500 Version 2 or newer cores. 65 */ 66 #define CONFIG_ENABLE_36BIT_PHYS 1 67 68 69 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 #define CONFIG_SYS_CCSRBAR 0xe0000000 75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 76 77 /* DDR Setup */ 78 #define CONFIG_FSL_DDR2 79 #undef CONFIG_FSL_DDR_INTERACTIVE 80 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 81 #define CONFIG_DDR_SPD 82 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 83 84 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 85 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_NUM_DDR_CONTROLLERS 1 90 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 91 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 92 93 /* I2C addresses of SPD EEPROMs */ 94 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 95 96 /* Make sure required options are set */ 97 #ifndef CONFIG_SPD_EEPROM 98 #error ("CONFIG_SPD_EEPROM is required") 99 #endif 100 101 #undef CONFIG_CLOCKS_IN_MHZ 102 103 /* 104 * Local Bus Definitions 105 */ 106 107 /* 108 * FLASH on the Local Bus 109 * Two banks, 8M each, using the CFI driver. 110 * Boot from BR0/OR0 bank at 0xff00_0000 111 * Alternate BR1/OR1 bank at 0xff80_0000 112 * 113 * BR0, BR1: 114 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 115 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 116 * Port Size = 16 bits = BRx[19:20] = 10 117 * Use GPCM = BRx[24:26] = 000 118 * Valid = BRx[31] = 1 119 * 120 * 0 4 8 12 16 20 24 28 121 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 122 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 123 * 124 * OR0, OR1: 125 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 126 * Reserved ORx[17:18] = 11, confusion here? 127 * CSNT = ORx[20] = 1 128 * ACS = half cycle delay = ORx[21:22] = 11 129 * SCY = 6 = ORx[24:27] = 0110 130 * TRLX = use relaxed timing = ORx[29] = 1 131 * EAD = use external address latch delay = OR[31] = 1 132 * 133 * 0 4 8 12 16 20 24 28 134 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 135 */ 136 #define CONFIG_SYS_BCSR_BASE 0xf8000000 137 138 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 139 140 /*Chip select 0 - Flash*/ 141 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 142 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 143 144 /*Chip slelect 1 - BCSR*/ 145 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 146 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 147 148 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 149 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 150 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 151 #undef CONFIG_SYS_FLASH_CHECKSUM 152 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 153 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 154 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 156 157 #define CONFIG_FLASH_CFI_DRIVER 158 #define CONFIG_SYS_FLASH_CFI 159 #define CONFIG_SYS_FLASH_EMPTY_INFO 160 161 162 /* 163 * SDRAM on the LocalBus 164 */ 165 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 166 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 167 168 169 /*Chip select 2 - SDRAM*/ 170 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 171 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 172 173 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 174 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 175 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 176 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 177 178 /* 179 * Common settings for all Local Bus SDRAM commands. 180 * At run time, either BSMA1516 (for CPU 1.1) 181 * or BSMA1617 (for CPU 1.0) (old) 182 * is OR'ed in too. 183 */ 184 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 185 | LSDMR_PRETOACT7 \ 186 | LSDMR_ACTTORW7 \ 187 | LSDMR_BL8 \ 188 | LSDMR_WRC4 \ 189 | LSDMR_CL3 \ 190 | LSDMR_RFEN \ 191 ) 192 193 /* 194 * The bcsr registers are connected to CS3 on MDS. 195 * The new memory map places bcsr at 0xf8000000. 196 * 197 * For BR3, need: 198 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 199 * port-size = 8-bits = BR[19:20] = 01 200 * no parity checking = BR[21:22] = 00 201 * GPMC for MSEL = BR[24:26] = 000 202 * Valid = BR[31] = 1 203 * 204 * 0 4 8 12 16 20 24 28 205 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 206 * 207 * For OR3, need: 208 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 209 * disable buffer ctrl OR[19] = 0 210 * CSNT OR[20] = 1 211 * ACS OR[21:22] = 11 212 * XACS OR[23] = 1 213 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 214 * SETA OR[28] = 0 215 * TRLX OR[29] = 1 216 * EHTR OR[30] = 1 217 * EAD extra time OR[31] = 1 218 * 219 * 0 4 8 12 16 20 24 28 220 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 221 */ 222 #define CONFIG_SYS_BCSR (0xf8000000) 223 224 /*Chip slelect 4 - PIB*/ 225 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 226 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 227 228 /*Chip select 5 - PIB*/ 229 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 230 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 231 232 #define CONFIG_SYS_INIT_RAM_LOCK 1 233 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 234 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 235 236 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 238 239 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 240 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 241 242 /* Serial Port */ 243 #define CONFIG_CONS_INDEX 1 244 #define CONFIG_SYS_NS16550 245 #define CONFIG_SYS_NS16550_SERIAL 246 #define CONFIG_SYS_NS16550_REG_SIZE 1 247 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 248 249 #define CONFIG_SYS_BAUDRATE_TABLE \ 250 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 251 252 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 253 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 254 255 /* Use the HUSH parser*/ 256 #define CONFIG_SYS_HUSH_PARSER 257 #ifdef CONFIG_SYS_HUSH_PARSER 258 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 259 #endif 260 261 /* pass open firmware flat tree */ 262 #define CONFIG_OF_LIBFDT 1 263 #define CONFIG_OF_BOARD_SETUP 1 264 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 265 266 /* 267 * I2C 268 */ 269 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 270 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 271 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 272 #define CONFIG_I2C_MULTI_BUS 273 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 274 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 275 #define CONFIG_SYS_I2C_SLAVE 0x7F 276 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 277 #define CONFIG_SYS_I2C_OFFSET 0x3000 278 #define CONFIG_SYS_I2C2_OFFSET 0x3100 279 280 /* 281 * General PCI 282 * Memory Addresses are mapped 1-1. I/O is mapped from 0 283 */ 284 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 285 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 286 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 287 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 288 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 289 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 290 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 291 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 292 293 #define CONFIG_SYS_PCIE1_NAME "Slot" 294 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 297 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 298 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 299 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 300 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 301 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 302 303 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 304 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 305 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 306 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 307 308 #ifdef CONFIG_QE 309 /* 310 * QE UEC ethernet configuration 311 */ 312 #define CONFIG_UEC_ETH 313 #ifndef CONFIG_TSEC_ENET 314 #define CONFIG_ETHPRIME "UEC0" 315 #endif 316 #define CONFIG_PHY_MODE_NEED_CHANGE 317 #define CONFIG_eTSEC_MDIO_BUS 318 319 #ifdef CONFIG_eTSEC_MDIO_BUS 320 #define CONFIG_MIIM_ADDRESS 0xE0024520 321 #endif 322 323 #define CONFIG_UEC_ETH1 /* GETH1 */ 324 325 #ifdef CONFIG_UEC_ETH1 326 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 327 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 328 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 329 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 330 #define CONFIG_SYS_UEC1_PHY_ADDR 7 331 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 332 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 333 #endif 334 335 #define CONFIG_UEC_ETH2 /* GETH2 */ 336 337 #ifdef CONFIG_UEC_ETH2 338 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 339 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 340 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 341 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 342 #define CONFIG_SYS_UEC2_PHY_ADDR 1 343 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 344 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 345 #endif 346 #endif /* CONFIG_QE */ 347 348 #if defined(CONFIG_PCI) 349 350 #define CONFIG_NET_MULTI 351 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 352 353 #undef CONFIG_EEPRO100 354 #undef CONFIG_TULIP 355 356 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 357 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 358 359 #endif /* CONFIG_PCI */ 360 361 #ifndef CONFIG_NET_MULTI 362 #define CONFIG_NET_MULTI 1 363 #endif 364 365 #if defined(CONFIG_TSEC_ENET) 366 367 #define CONFIG_MII 1 /* MII PHY management */ 368 #define CONFIG_TSEC1 1 369 #define CONFIG_TSEC1_NAME "eTSEC0" 370 #define CONFIG_TSEC2 1 371 #define CONFIG_TSEC2_NAME "eTSEC1" 372 373 #define TSEC1_PHY_ADDR 2 374 #define TSEC2_PHY_ADDR 3 375 376 #define TSEC1_PHYIDX 0 377 #define TSEC2_PHYIDX 0 378 379 #define TSEC1_FLAGS TSEC_GIGABIT 380 #define TSEC2_FLAGS TSEC_GIGABIT 381 382 /* Options are: eTSEC[0-1] */ 383 #define CONFIG_ETHPRIME "eTSEC0" 384 385 #endif /* CONFIG_TSEC_ENET */ 386 387 /* 388 * Environment 389 */ 390 #define CONFIG_ENV_IS_IN_FLASH 1 391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 392 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 393 #define CONFIG_ENV_SIZE 0x2000 394 395 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 397 398 399 /* 400 * BOOTP options 401 */ 402 #define CONFIG_BOOTP_BOOTFILESIZE 403 #define CONFIG_BOOTP_BOOTPATH 404 #define CONFIG_BOOTP_GATEWAY 405 #define CONFIG_BOOTP_HOSTNAME 406 407 408 /* 409 * Command line configuration. 410 */ 411 #include <config_cmd_default.h> 412 413 #define CONFIG_CMD_PING 414 #define CONFIG_CMD_I2C 415 #define CONFIG_CMD_MII 416 #define CONFIG_CMD_ELF 417 #define CONFIG_CMD_IRQ 418 #define CONFIG_CMD_SETEXPR 419 #define CONFIG_CMD_REGINFO 420 421 #if defined(CONFIG_PCI) 422 #define CONFIG_CMD_PCI 423 #endif 424 425 426 #undef CONFIG_WATCHDOG /* watchdog disabled */ 427 428 /* 429 * Miscellaneous configurable options 430 */ 431 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 432 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 433 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 434 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 435 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 436 #if defined(CONFIG_CMD_KGDB) 437 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 438 #else 439 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 440 #endif 441 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 442 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 443 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 444 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 445 446 /* 447 * For booting Linux, the board info and command line data 448 * have to be in the first 64 MB of memory, since this is 449 * the maximum mapped by the Linux kernel during initialization. 450 */ 451 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 452 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 453 454 #if defined(CONFIG_CMD_KGDB) 455 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 456 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 457 #endif 458 459 /* 460 * Environment Configuration 461 */ 462 463 /* The mac addresses for all ethernet interface */ 464 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 465 #define CONFIG_HAS_ETH0 466 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 467 #define CONFIG_HAS_ETH1 468 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 469 #define CONFIG_HAS_ETH2 470 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 471 #define CONFIG_HAS_ETH3 472 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 473 #endif 474 475 #define CONFIG_IPADDR 192.168.1.253 476 477 #define CONFIG_HOSTNAME unknown 478 #define CONFIG_ROOTPATH /nfsroot 479 #define CONFIG_BOOTFILE your.uImage 480 481 #define CONFIG_SERVERIP 192.168.1.1 482 #define CONFIG_GATEWAYIP 192.168.1.1 483 #define CONFIG_NETMASK 255.255.255.0 484 485 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 486 487 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 488 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 489 490 #define CONFIG_BAUDRATE 115200 491 492 #define CONFIG_EXTRA_ENV_SETTINGS \ 493 "netdev=eth0\0" \ 494 "consoledev=ttyS0\0" \ 495 "ramdiskaddr=600000\0" \ 496 "ramdiskfile=your.ramdisk.u-boot\0" \ 497 "fdtaddr=400000\0" \ 498 "fdtfile=your.fdt.dtb\0" \ 499 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 500 "nfsroot=$serverip:$rootpath " \ 501 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 502 "console=$consoledev,$baudrate $othbootargs\0" \ 503 "ramargs=setenv bootargs root=/dev/ram rw " \ 504 "console=$consoledev,$baudrate $othbootargs\0" \ 505 506 507 #define CONFIG_NFSBOOTCOMMAND \ 508 "run nfsargs;" \ 509 "tftp $loadaddr $bootfile;" \ 510 "tftp $fdtaddr $fdtfile;" \ 511 "bootm $loadaddr - $fdtaddr" 512 513 514 #define CONFIG_RAMBOOTCOMMAND \ 515 "run ramargs;" \ 516 "tftp $ramdiskaddr $ramdiskfile;" \ 517 "tftp $loadaddr $bootfile;" \ 518 "bootm $loadaddr $ramdiskaddr" 519 520 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 521 522 #endif /* __CONFIG_H */ 523