1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8568mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_SRIO 14 #define CONFIG_SRIO1 /* SRIO port 1 */ 15 16 #define CONFIG_PCI1 1 /* PCI controller */ 17 #define CONFIG_PCIE1 1 /* PCIE controller */ 18 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 19 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 20 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 21 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 22 #define CONFIG_QE /* Enable QE */ 23 #define CONFIG_ENV_OVERWRITE 24 25 #ifndef __ASSEMBLY__ 26 extern unsigned long get_clock_freq(void); 27 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 28 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 29 30 /* 31 * These can be toggled for performance analysis, otherwise use default. 32 */ 33 #define CONFIG_L2_CACHE /* toggle L2 cache */ 34 #define CONFIG_BTB /* toggle branch predition */ 35 36 /* 37 * Only possible on E500 Version 2 or newer cores. 38 */ 39 #define CONFIG_ENABLE_36BIT_PHYS 1 40 41 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 42 #define CONFIG_SYS_MEMTEST_END 0x00400000 43 44 #define CONFIG_SYS_CCSRBAR 0xe0000000 45 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 46 47 /* DDR Setup */ 48 #undef CONFIG_FSL_DDR_INTERACTIVE 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 50 #define CONFIG_DDR_SPD 51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 52 53 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 54 55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 57 58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 59 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 60 61 /* I2C addresses of SPD EEPROMs */ 62 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 63 64 /* Make sure required options are set */ 65 #ifndef CONFIG_SPD_EEPROM 66 #error ("CONFIG_SPD_EEPROM is required") 67 #endif 68 69 #undef CONFIG_CLOCKS_IN_MHZ 70 71 /* 72 * Local Bus Definitions 73 */ 74 75 /* 76 * FLASH on the Local Bus 77 * Two banks, 8M each, using the CFI driver. 78 * Boot from BR0/OR0 bank at 0xff00_0000 79 * Alternate BR1/OR1 bank at 0xff80_0000 80 * 81 * BR0, BR1: 82 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 83 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 84 * Port Size = 16 bits = BRx[19:20] = 10 85 * Use GPCM = BRx[24:26] = 000 86 * Valid = BRx[31] = 1 87 * 88 * 0 4 8 12 16 20 24 28 89 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 90 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 91 * 92 * OR0, OR1: 93 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 94 * Reserved ORx[17:18] = 11, confusion here? 95 * CSNT = ORx[20] = 1 96 * ACS = half cycle delay = ORx[21:22] = 11 97 * SCY = 6 = ORx[24:27] = 0110 98 * TRLX = use relaxed timing = ORx[29] = 1 99 * EAD = use external address latch delay = OR[31] = 1 100 * 101 * 0 4 8 12 16 20 24 28 102 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 103 */ 104 #define CONFIG_SYS_BCSR_BASE 0xf8000000 105 106 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 107 108 /*Chip select 0 - Flash*/ 109 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 110 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 111 112 /*Chip slelect 1 - BCSR*/ 113 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 114 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 115 116 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 119 #undef CONFIG_SYS_FLASH_CHECKSUM 120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 124 125 #define CONFIG_FLASH_CFI_DRIVER 126 #define CONFIG_SYS_FLASH_CFI 127 #define CONFIG_SYS_FLASH_EMPTY_INFO 128 129 /* 130 * SDRAM on the LocalBus 131 */ 132 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 133 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 134 135 /*Chip select 2 - SDRAM*/ 136 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 137 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 138 139 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 140 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 141 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 142 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 143 144 /* 145 * Common settings for all Local Bus SDRAM commands. 146 * At run time, either BSMA1516 (for CPU 1.1) 147 * or BSMA1617 (for CPU 1.0) (old) 148 * is OR'ed in too. 149 */ 150 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 151 | LSDMR_PRETOACT7 \ 152 | LSDMR_ACTTORW7 \ 153 | LSDMR_BL8 \ 154 | LSDMR_WRC4 \ 155 | LSDMR_CL3 \ 156 | LSDMR_RFEN \ 157 ) 158 159 /* 160 * The bcsr registers are connected to CS3 on MDS. 161 * The new memory map places bcsr at 0xf8000000. 162 * 163 * For BR3, need: 164 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 165 * port-size = 8-bits = BR[19:20] = 01 166 * no parity checking = BR[21:22] = 00 167 * GPMC for MSEL = BR[24:26] = 000 168 * Valid = BR[31] = 1 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 172 * 173 * For OR3, need: 174 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 175 * disable buffer ctrl OR[19] = 0 176 * CSNT OR[20] = 1 177 * ACS OR[21:22] = 11 178 * XACS OR[23] = 1 179 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 180 * SETA OR[28] = 0 181 * TRLX OR[29] = 1 182 * EHTR OR[30] = 1 183 * EAD extra time OR[31] = 1 184 * 185 * 0 4 8 12 16 20 24 28 186 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 187 */ 188 #define CONFIG_SYS_BCSR (0xf8000000) 189 190 /*Chip slelect 4 - PIB*/ 191 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 192 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 193 194 /*Chip select 5 - PIB*/ 195 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 196 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 197 198 #define CONFIG_SYS_INIT_RAM_LOCK 1 199 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 201 202 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 203 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 204 205 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 206 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 207 208 /* Serial Port */ 209 #define CONFIG_SYS_NS16550_SERIAL 210 #define CONFIG_SYS_NS16550_REG_SIZE 1 211 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 212 213 #define CONFIG_SYS_BAUDRATE_TABLE \ 214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 215 216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 217 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 218 219 /* 220 * I2C 221 */ 222 #define CONFIG_SYS_I2C 223 #define CONFIG_SYS_I2C_FSL 224 #define CONFIG_SYS_FSL_I2C_SPEED 400000 225 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 226 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 227 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 228 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 229 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 230 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 231 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 232 233 /* 234 * General PCI 235 * Memory Addresses are mapped 1-1. I/O is mapped from 0 236 */ 237 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 238 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 239 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 240 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 241 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 242 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 243 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 244 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 245 246 #define CONFIG_SYS_PCIE1_NAME "Slot" 247 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 248 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 249 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 250 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 251 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 252 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 253 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 254 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 255 256 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 257 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 258 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 259 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 260 261 #ifdef CONFIG_QE 262 /* 263 * QE UEC ethernet configuration 264 */ 265 #define CONFIG_UEC_ETH 266 #ifndef CONFIG_TSEC_ENET 267 #define CONFIG_ETHPRIME "UEC0" 268 #endif 269 #define CONFIG_PHY_MODE_NEED_CHANGE 270 #define CONFIG_eTSEC_MDIO_BUS 271 272 #ifdef CONFIG_eTSEC_MDIO_BUS 273 #define CONFIG_MIIM_ADDRESS 0xE0024520 274 #endif 275 276 #define CONFIG_UEC_ETH1 /* GETH1 */ 277 278 #ifdef CONFIG_UEC_ETH1 279 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 280 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 281 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 282 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 283 #define CONFIG_SYS_UEC1_PHY_ADDR 7 284 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 285 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 286 #endif 287 288 #define CONFIG_UEC_ETH2 /* GETH2 */ 289 290 #ifdef CONFIG_UEC_ETH2 291 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 292 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 293 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 294 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 295 #define CONFIG_SYS_UEC2_PHY_ADDR 1 296 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 297 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 298 #endif 299 #endif /* CONFIG_QE */ 300 301 #if defined(CONFIG_PCI) 302 #undef CONFIG_EEPRO100 303 #undef CONFIG_TULIP 304 305 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 306 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 307 308 #endif /* CONFIG_PCI */ 309 310 #if defined(CONFIG_TSEC_ENET) 311 312 #define CONFIG_MII 1 /* MII PHY management */ 313 #define CONFIG_TSEC1 1 314 #define CONFIG_TSEC1_NAME "eTSEC0" 315 #define CONFIG_TSEC2 1 316 #define CONFIG_TSEC2_NAME "eTSEC1" 317 318 #define TSEC1_PHY_ADDR 2 319 #define TSEC2_PHY_ADDR 3 320 321 #define TSEC1_PHYIDX 0 322 #define TSEC2_PHYIDX 0 323 324 #define TSEC1_FLAGS TSEC_GIGABIT 325 #define TSEC2_FLAGS TSEC_GIGABIT 326 327 /* Options are: eTSEC[0-1] */ 328 #define CONFIG_ETHPRIME "eTSEC0" 329 330 #endif /* CONFIG_TSEC_ENET */ 331 332 /* 333 * Environment 334 */ 335 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 336 #define CONFIG_ENV_SIZE 0x2000 337 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 338 339 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 340 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 341 342 /* 343 * BOOTP options 344 */ 345 #define CONFIG_BOOTP_BOOTFILESIZE 346 347 #undef CONFIG_WATCHDOG /* watchdog disabled */ 348 349 /* 350 * Miscellaneous configurable options 351 */ 352 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 353 354 /* 355 * For booting Linux, the board info and command line data 356 * have to be in the first 64 MB of memory, since this is 357 * the maximum mapped by the Linux kernel during initialization. 358 */ 359 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 360 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 361 362 #if defined(CONFIG_CMD_KGDB) 363 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 364 #endif 365 366 /* 367 * Environment Configuration 368 */ 369 370 /* The mac addresses for all ethernet interface */ 371 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 372 #define CONFIG_HAS_ETH0 373 #define CONFIG_HAS_ETH1 374 #define CONFIG_HAS_ETH2 375 #define CONFIG_HAS_ETH3 376 #endif 377 378 #define CONFIG_IPADDR 192.168.1.253 379 380 #define CONFIG_HOSTNAME "unknown" 381 #define CONFIG_ROOTPATH "/nfsroot" 382 #define CONFIG_BOOTFILE "your.uImage" 383 384 #define CONFIG_SERVERIP 192.168.1.1 385 #define CONFIG_GATEWAYIP 192.168.1.1 386 #define CONFIG_NETMASK 255.255.255.0 387 388 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 389 390 #define CONFIG_EXTRA_ENV_SETTINGS \ 391 "netdev=eth0\0" \ 392 "consoledev=ttyS0\0" \ 393 "ramdiskaddr=600000\0" \ 394 "ramdiskfile=your.ramdisk.u-boot\0" \ 395 "fdtaddr=400000\0" \ 396 "fdtfile=your.fdt.dtb\0" \ 397 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 398 "nfsroot=$serverip:$rootpath " \ 399 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 400 "console=$consoledev,$baudrate $othbootargs\0" \ 401 "ramargs=setenv bootargs root=/dev/ram rw " \ 402 "console=$consoledev,$baudrate $othbootargs\0" \ 403 404 #define CONFIG_NFSBOOTCOMMAND \ 405 "run nfsargs;" \ 406 "tftp $loadaddr $bootfile;" \ 407 "tftp $fdtaddr $fdtfile;" \ 408 "bootm $loadaddr - $fdtaddr" 409 410 #define CONFIG_RAMBOOTCOMMAND \ 411 "run ramargs;" \ 412 "tftp $ramdiskaddr $ramdiskfile;" \ 413 "tftp $loadaddr $bootfile;" \ 414 "bootm $loadaddr $ramdiskaddr" 415 416 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 417 418 #endif /* __CONFIG_H */ 419