1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8568mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 17 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 18 19 #define CONFIG_SYS_TEXT_BASE 0xfff80000 20 21 #define CONFIG_SYS_SRIO 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 24 #define CONFIG_PCI1 1 /* PCI controller */ 25 #define CONFIG_PCIE1 1 /* PCIE controller */ 26 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 28 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 31 #define CONFIG_QE /* Enable QE */ 32 #define CONFIG_ENV_OVERWRITE 33 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 34 35 #ifndef __ASSEMBLY__ 36 extern unsigned long get_clock_freq(void); 37 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 38 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 39 40 /* 41 * These can be toggled for performance analysis, otherwise use default. 42 */ 43 #define CONFIG_L2_CACHE /* toggle L2 cache */ 44 #define CONFIG_BTB /* toggle branch predition */ 45 46 /* 47 * Only possible on E500 Version 2 or newer cores. 48 */ 49 #define CONFIG_ENABLE_36BIT_PHYS 1 50 51 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 52 53 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 54 #define CONFIG_SYS_MEMTEST_END 0x00400000 55 56 #define CONFIG_SYS_CCSRBAR 0xe0000000 57 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 58 59 /* DDR Setup */ 60 #define CONFIG_SYS_FSL_DDR2 61 #undef CONFIG_FSL_DDR_INTERACTIVE 62 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 63 #define CONFIG_DDR_SPD 64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 65 66 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 67 68 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 70 71 #define CONFIG_NUM_DDR_CONTROLLERS 1 72 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 73 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 74 75 /* I2C addresses of SPD EEPROMs */ 76 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 77 78 /* Make sure required options are set */ 79 #ifndef CONFIG_SPD_EEPROM 80 #error ("CONFIG_SPD_EEPROM is required") 81 #endif 82 83 #undef CONFIG_CLOCKS_IN_MHZ 84 85 /* 86 * Local Bus Definitions 87 */ 88 89 /* 90 * FLASH on the Local Bus 91 * Two banks, 8M each, using the CFI driver. 92 * Boot from BR0/OR0 bank at 0xff00_0000 93 * Alternate BR1/OR1 bank at 0xff80_0000 94 * 95 * BR0, BR1: 96 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 97 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 98 * Port Size = 16 bits = BRx[19:20] = 10 99 * Use GPCM = BRx[24:26] = 000 100 * Valid = BRx[31] = 1 101 * 102 * 0 4 8 12 16 20 24 28 103 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 104 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 105 * 106 * OR0, OR1: 107 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 108 * Reserved ORx[17:18] = 11, confusion here? 109 * CSNT = ORx[20] = 1 110 * ACS = half cycle delay = ORx[21:22] = 11 111 * SCY = 6 = ORx[24:27] = 0110 112 * TRLX = use relaxed timing = ORx[29] = 1 113 * EAD = use external address latch delay = OR[31] = 1 114 * 115 * 0 4 8 12 16 20 24 28 116 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 117 */ 118 #define CONFIG_SYS_BCSR_BASE 0xf8000000 119 120 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 121 122 /*Chip select 0 - Flash*/ 123 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 124 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 125 126 /*Chip slelect 1 - BCSR*/ 127 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 128 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 129 130 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 132 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 133 #undef CONFIG_SYS_FLASH_CHECKSUM 134 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 136 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 138 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_EMPTY_INFO 142 143 /* 144 * SDRAM on the LocalBus 145 */ 146 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 147 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 148 149 /*Chip select 2 - SDRAM*/ 150 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 151 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 152 153 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 154 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 155 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 156 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 157 158 /* 159 * Common settings for all Local Bus SDRAM commands. 160 * At run time, either BSMA1516 (for CPU 1.1) 161 * or BSMA1617 (for CPU 1.0) (old) 162 * is OR'ed in too. 163 */ 164 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 165 | LSDMR_PRETOACT7 \ 166 | LSDMR_ACTTORW7 \ 167 | LSDMR_BL8 \ 168 | LSDMR_WRC4 \ 169 | LSDMR_CL3 \ 170 | LSDMR_RFEN \ 171 ) 172 173 /* 174 * The bcsr registers are connected to CS3 on MDS. 175 * The new memory map places bcsr at 0xf8000000. 176 * 177 * For BR3, need: 178 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 179 * port-size = 8-bits = BR[19:20] = 01 180 * no parity checking = BR[21:22] = 00 181 * GPMC for MSEL = BR[24:26] = 000 182 * Valid = BR[31] = 1 183 * 184 * 0 4 8 12 16 20 24 28 185 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 186 * 187 * For OR3, need: 188 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 189 * disable buffer ctrl OR[19] = 0 190 * CSNT OR[20] = 1 191 * ACS OR[21:22] = 11 192 * XACS OR[23] = 1 193 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 194 * SETA OR[28] = 0 195 * TRLX OR[29] = 1 196 * EHTR OR[30] = 1 197 * EAD extra time OR[31] = 1 198 * 199 * 0 4 8 12 16 20 24 28 200 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 201 */ 202 #define CONFIG_SYS_BCSR (0xf8000000) 203 204 /*Chip slelect 4 - PIB*/ 205 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 206 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 207 208 /*Chip select 5 - PIB*/ 209 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 210 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 211 212 #define CONFIG_SYS_INIT_RAM_LOCK 1 213 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 214 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 215 216 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 217 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 218 219 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 220 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 221 222 /* Serial Port */ 223 #define CONFIG_CONS_INDEX 1 224 #define CONFIG_SYS_NS16550_SERIAL 225 #define CONFIG_SYS_NS16550_REG_SIZE 1 226 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 227 228 #define CONFIG_SYS_BAUDRATE_TABLE \ 229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 230 231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 232 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 233 234 /* 235 * I2C 236 */ 237 #define CONFIG_SYS_I2C 238 #define CONFIG_SYS_I2C_FSL 239 #define CONFIG_SYS_FSL_I2C_SPEED 400000 240 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 241 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 242 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 243 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 244 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 245 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 246 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 247 248 /* 249 * General PCI 250 * Memory Addresses are mapped 1-1. I/O is mapped from 0 251 */ 252 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 253 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 254 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 255 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 256 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 257 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 258 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 259 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 260 261 #define CONFIG_SYS_PCIE1_NAME "Slot" 262 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 263 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 264 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 265 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 266 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 267 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 268 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 269 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 270 271 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 272 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 273 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 274 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 275 276 #ifdef CONFIG_QE 277 /* 278 * QE UEC ethernet configuration 279 */ 280 #define CONFIG_UEC_ETH 281 #ifndef CONFIG_TSEC_ENET 282 #define CONFIG_ETHPRIME "UEC0" 283 #endif 284 #define CONFIG_PHY_MODE_NEED_CHANGE 285 #define CONFIG_eTSEC_MDIO_BUS 286 287 #ifdef CONFIG_eTSEC_MDIO_BUS 288 #define CONFIG_MIIM_ADDRESS 0xE0024520 289 #endif 290 291 #define CONFIG_UEC_ETH1 /* GETH1 */ 292 293 #ifdef CONFIG_UEC_ETH1 294 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 295 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 296 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 297 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 298 #define CONFIG_SYS_UEC1_PHY_ADDR 7 299 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 300 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 301 #endif 302 303 #define CONFIG_UEC_ETH2 /* GETH2 */ 304 305 #ifdef CONFIG_UEC_ETH2 306 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 307 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 308 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 309 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 310 #define CONFIG_SYS_UEC2_PHY_ADDR 1 311 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 312 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 313 #endif 314 #endif /* CONFIG_QE */ 315 316 #if defined(CONFIG_PCI) 317 #undef CONFIG_EEPRO100 318 #undef CONFIG_TULIP 319 320 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 321 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 322 323 #endif /* CONFIG_PCI */ 324 325 #if defined(CONFIG_TSEC_ENET) 326 327 #define CONFIG_MII 1 /* MII PHY management */ 328 #define CONFIG_TSEC1 1 329 #define CONFIG_TSEC1_NAME "eTSEC0" 330 #define CONFIG_TSEC2 1 331 #define CONFIG_TSEC2_NAME "eTSEC1" 332 333 #define TSEC1_PHY_ADDR 2 334 #define TSEC2_PHY_ADDR 3 335 336 #define TSEC1_PHYIDX 0 337 #define TSEC2_PHYIDX 0 338 339 #define TSEC1_FLAGS TSEC_GIGABIT 340 #define TSEC2_FLAGS TSEC_GIGABIT 341 342 /* Options are: eTSEC[0-1] */ 343 #define CONFIG_ETHPRIME "eTSEC0" 344 345 #endif /* CONFIG_TSEC_ENET */ 346 347 /* 348 * Environment 349 */ 350 #define CONFIG_ENV_IS_IN_FLASH 1 351 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 352 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 353 #define CONFIG_ENV_SIZE 0x2000 354 355 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 356 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 357 358 /* 359 * BOOTP options 360 */ 361 #define CONFIG_BOOTP_BOOTFILESIZE 362 #define CONFIG_BOOTP_BOOTPATH 363 #define CONFIG_BOOTP_GATEWAY 364 #define CONFIG_BOOTP_HOSTNAME 365 366 /* 367 * Command line configuration. 368 */ 369 #define CONFIG_CMD_IRQ 370 #define CONFIG_CMD_REGINFO 371 372 #if defined(CONFIG_PCI) 373 #define CONFIG_CMD_PCI 374 #endif 375 376 #undef CONFIG_WATCHDOG /* watchdog disabled */ 377 378 /* 379 * Miscellaneous configurable options 380 */ 381 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 382 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 383 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 384 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 385 #if defined(CONFIG_CMD_KGDB) 386 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 387 #else 388 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 389 #endif 390 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 391 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 392 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 393 394 /* 395 * For booting Linux, the board info and command line data 396 * have to be in the first 64 MB of memory, since this is 397 * the maximum mapped by the Linux kernel during initialization. 398 */ 399 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 400 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 401 402 #if defined(CONFIG_CMD_KGDB) 403 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 404 #endif 405 406 /* 407 * Environment Configuration 408 */ 409 410 /* The mac addresses for all ethernet interface */ 411 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 412 #define CONFIG_HAS_ETH0 413 #define CONFIG_HAS_ETH1 414 #define CONFIG_HAS_ETH2 415 #define CONFIG_HAS_ETH3 416 #endif 417 418 #define CONFIG_IPADDR 192.168.1.253 419 420 #define CONFIG_HOSTNAME unknown 421 #define CONFIG_ROOTPATH "/nfsroot" 422 #define CONFIG_BOOTFILE "your.uImage" 423 424 #define CONFIG_SERVERIP 192.168.1.1 425 #define CONFIG_GATEWAYIP 192.168.1.1 426 #define CONFIG_NETMASK 255.255.255.0 427 428 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 429 430 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 431 432 #define CONFIG_BAUDRATE 115200 433 434 #define CONFIG_EXTRA_ENV_SETTINGS \ 435 "netdev=eth0\0" \ 436 "consoledev=ttyS0\0" \ 437 "ramdiskaddr=600000\0" \ 438 "ramdiskfile=your.ramdisk.u-boot\0" \ 439 "fdtaddr=400000\0" \ 440 "fdtfile=your.fdt.dtb\0" \ 441 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 442 "nfsroot=$serverip:$rootpath " \ 443 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 444 "console=$consoledev,$baudrate $othbootargs\0" \ 445 "ramargs=setenv bootargs root=/dev/ram rw " \ 446 "console=$consoledev,$baudrate $othbootargs\0" \ 447 448 #define CONFIG_NFSBOOTCOMMAND \ 449 "run nfsargs;" \ 450 "tftp $loadaddr $bootfile;" \ 451 "tftp $fdtaddr $fdtfile;" \ 452 "bootm $loadaddr - $fdtaddr" 453 454 #define CONFIG_RAMBOOTCOMMAND \ 455 "run ramargs;" \ 456 "tftp $ramdiskaddr $ramdiskfile;" \ 457 "tftp $loadaddr $bootfile;" \ 458 "bootm $loadaddr $ramdiskaddr" 459 460 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 461 462 #endif /* __CONFIG_H */ 463