1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8568mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 20 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 21 22 #define CONFIG_SYS_TEXT_BASE 0xfff80000 23 24 #define CONFIG_SYS_SRIO 25 #define CONFIG_SRIO1 /* SRIO port 1 */ 26 27 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 28 #define CONFIG_PCI1 1 /* PCI controller */ 29 #define CONFIG_PCIE1 1 /* PCIE controller */ 30 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 35 #define CONFIG_QE /* Enable QE */ 36 #define CONFIG_ENV_OVERWRITE 37 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 38 39 #ifndef __ASSEMBLY__ 40 extern unsigned long get_clock_freq(void); 41 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 42 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 43 44 /* 45 * These can be toggled for performance analysis, otherwise use default. 46 */ 47 #define CONFIG_L2_CACHE /* toggle L2 cache */ 48 #define CONFIG_BTB /* toggle branch predition */ 49 50 /* 51 * Only possible on E500 Version 2 or newer cores. 52 */ 53 #define CONFIG_ENABLE_36BIT_PHYS 1 54 55 56 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 57 58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 59 #define CONFIG_SYS_MEMTEST_END 0x00400000 60 61 #define CONFIG_SYS_CCSRBAR 0xe0000000 62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 63 64 /* DDR Setup */ 65 #define CONFIG_SYS_FSL_DDR2 66 #undef CONFIG_FSL_DDR_INTERACTIVE 67 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 68 #define CONFIG_DDR_SPD 69 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 70 71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 72 73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 75 76 #define CONFIG_NUM_DDR_CONTROLLERS 1 77 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 78 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 79 80 /* I2C addresses of SPD EEPROMs */ 81 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 82 83 /* Make sure required options are set */ 84 #ifndef CONFIG_SPD_EEPROM 85 #error ("CONFIG_SPD_EEPROM is required") 86 #endif 87 88 #undef CONFIG_CLOCKS_IN_MHZ 89 90 /* 91 * Local Bus Definitions 92 */ 93 94 /* 95 * FLASH on the Local Bus 96 * Two banks, 8M each, using the CFI driver. 97 * Boot from BR0/OR0 bank at 0xff00_0000 98 * Alternate BR1/OR1 bank at 0xff80_0000 99 * 100 * BR0, BR1: 101 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 102 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 103 * Port Size = 16 bits = BRx[19:20] = 10 104 * Use GPCM = BRx[24:26] = 000 105 * Valid = BRx[31] = 1 106 * 107 * 0 4 8 12 16 20 24 28 108 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 109 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 110 * 111 * OR0, OR1: 112 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 113 * Reserved ORx[17:18] = 11, confusion here? 114 * CSNT = ORx[20] = 1 115 * ACS = half cycle delay = ORx[21:22] = 11 116 * SCY = 6 = ORx[24:27] = 0110 117 * TRLX = use relaxed timing = ORx[29] = 1 118 * EAD = use external address latch delay = OR[31] = 1 119 * 120 * 0 4 8 12 16 20 24 28 121 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 122 */ 123 #define CONFIG_SYS_BCSR_BASE 0xf8000000 124 125 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 126 127 /*Chip select 0 - Flash*/ 128 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 129 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 130 131 /*Chip slelect 1 - BCSR*/ 132 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 133 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 134 135 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 136 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 137 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 138 #undef CONFIG_SYS_FLASH_CHECKSUM 139 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 140 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 141 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 143 144 #define CONFIG_FLASH_CFI_DRIVER 145 #define CONFIG_SYS_FLASH_CFI 146 #define CONFIG_SYS_FLASH_EMPTY_INFO 147 148 149 /* 150 * SDRAM on the LocalBus 151 */ 152 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 153 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 154 155 156 /*Chip select 2 - SDRAM*/ 157 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 158 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 159 160 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 161 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 162 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 163 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 164 165 /* 166 * Common settings for all Local Bus SDRAM commands. 167 * At run time, either BSMA1516 (for CPU 1.1) 168 * or BSMA1617 (for CPU 1.0) (old) 169 * is OR'ed in too. 170 */ 171 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 172 | LSDMR_PRETOACT7 \ 173 | LSDMR_ACTTORW7 \ 174 | LSDMR_BL8 \ 175 | LSDMR_WRC4 \ 176 | LSDMR_CL3 \ 177 | LSDMR_RFEN \ 178 ) 179 180 /* 181 * The bcsr registers are connected to CS3 on MDS. 182 * The new memory map places bcsr at 0xf8000000. 183 * 184 * For BR3, need: 185 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 186 * port-size = 8-bits = BR[19:20] = 01 187 * no parity checking = BR[21:22] = 00 188 * GPMC for MSEL = BR[24:26] = 000 189 * Valid = BR[31] = 1 190 * 191 * 0 4 8 12 16 20 24 28 192 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 193 * 194 * For OR3, need: 195 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 196 * disable buffer ctrl OR[19] = 0 197 * CSNT OR[20] = 1 198 * ACS OR[21:22] = 11 199 * XACS OR[23] = 1 200 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 201 * SETA OR[28] = 0 202 * TRLX OR[29] = 1 203 * EHTR OR[30] = 1 204 * EAD extra time OR[31] = 1 205 * 206 * 0 4 8 12 16 20 24 28 207 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 208 */ 209 #define CONFIG_SYS_BCSR (0xf8000000) 210 211 /*Chip slelect 4 - PIB*/ 212 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 213 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 214 215 /*Chip select 5 - PIB*/ 216 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 217 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 218 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 221 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 222 223 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 224 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 225 226 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 227 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 228 229 /* Serial Port */ 230 #define CONFIG_CONS_INDEX 1 231 #define CONFIG_SYS_NS16550 232 #define CONFIG_SYS_NS16550_SERIAL 233 #define CONFIG_SYS_NS16550_REG_SIZE 1 234 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 235 236 #define CONFIG_SYS_BAUDRATE_TABLE \ 237 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 238 239 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 240 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 241 242 /* Use the HUSH parser*/ 243 #define CONFIG_SYS_HUSH_PARSER 244 #ifdef CONFIG_SYS_HUSH_PARSER 245 #endif 246 247 /* pass open firmware flat tree */ 248 #define CONFIG_OF_LIBFDT 1 249 #define CONFIG_OF_BOARD_SETUP 1 250 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 251 252 /* 253 * I2C 254 */ 255 #define CONFIG_SYS_I2C 256 #define CONFIG_SYS_I2C_FSL 257 #define CONFIG_SYS_FSL_I2C_SPEED 400000 258 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 259 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 260 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 261 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 262 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 263 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 264 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 265 266 /* 267 * General PCI 268 * Memory Addresses are mapped 1-1. I/O is mapped from 0 269 */ 270 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 271 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 272 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 273 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 274 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 275 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 276 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 277 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 278 279 #define CONFIG_SYS_PCIE1_NAME "Slot" 280 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 281 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 282 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 283 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 284 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 285 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 286 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 287 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 288 289 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 290 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 291 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 292 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 293 294 #ifdef CONFIG_QE 295 /* 296 * QE UEC ethernet configuration 297 */ 298 #define CONFIG_UEC_ETH 299 #ifndef CONFIG_TSEC_ENET 300 #define CONFIG_ETHPRIME "UEC0" 301 #endif 302 #define CONFIG_PHY_MODE_NEED_CHANGE 303 #define CONFIG_eTSEC_MDIO_BUS 304 305 #ifdef CONFIG_eTSEC_MDIO_BUS 306 #define CONFIG_MIIM_ADDRESS 0xE0024520 307 #endif 308 309 #define CONFIG_UEC_ETH1 /* GETH1 */ 310 311 #ifdef CONFIG_UEC_ETH1 312 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 313 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 314 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 315 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 316 #define CONFIG_SYS_UEC1_PHY_ADDR 7 317 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 318 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 319 #endif 320 321 #define CONFIG_UEC_ETH2 /* GETH2 */ 322 323 #ifdef CONFIG_UEC_ETH2 324 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 325 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 326 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 327 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 328 #define CONFIG_SYS_UEC2_PHY_ADDR 1 329 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 330 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 331 #endif 332 #endif /* CONFIG_QE */ 333 334 #if defined(CONFIG_PCI) 335 336 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 337 338 #undef CONFIG_EEPRO100 339 #undef CONFIG_TULIP 340 341 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 342 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 343 344 #endif /* CONFIG_PCI */ 345 346 #if defined(CONFIG_TSEC_ENET) 347 348 #define CONFIG_MII 1 /* MII PHY management */ 349 #define CONFIG_TSEC1 1 350 #define CONFIG_TSEC1_NAME "eTSEC0" 351 #define CONFIG_TSEC2 1 352 #define CONFIG_TSEC2_NAME "eTSEC1" 353 354 #define TSEC1_PHY_ADDR 2 355 #define TSEC2_PHY_ADDR 3 356 357 #define TSEC1_PHYIDX 0 358 #define TSEC2_PHYIDX 0 359 360 #define TSEC1_FLAGS TSEC_GIGABIT 361 #define TSEC2_FLAGS TSEC_GIGABIT 362 363 /* Options are: eTSEC[0-1] */ 364 #define CONFIG_ETHPRIME "eTSEC0" 365 366 #endif /* CONFIG_TSEC_ENET */ 367 368 /* 369 * Environment 370 */ 371 #define CONFIG_ENV_IS_IN_FLASH 1 372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 373 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 374 #define CONFIG_ENV_SIZE 0x2000 375 376 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 377 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 378 379 380 /* 381 * BOOTP options 382 */ 383 #define CONFIG_BOOTP_BOOTFILESIZE 384 #define CONFIG_BOOTP_BOOTPATH 385 #define CONFIG_BOOTP_GATEWAY 386 #define CONFIG_BOOTP_HOSTNAME 387 388 389 /* 390 * Command line configuration. 391 */ 392 #define CONFIG_CMD_PING 393 #define CONFIG_CMD_I2C 394 #define CONFIG_CMD_MII 395 #define CONFIG_CMD_IRQ 396 #define CONFIG_CMD_REGINFO 397 398 #if defined(CONFIG_PCI) 399 #define CONFIG_CMD_PCI 400 #endif 401 402 403 #undef CONFIG_WATCHDOG /* watchdog disabled */ 404 405 /* 406 * Miscellaneous configurable options 407 */ 408 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 409 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 410 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 411 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 412 #if defined(CONFIG_CMD_KGDB) 413 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 414 #else 415 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 416 #endif 417 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 418 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 419 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 420 421 /* 422 * For booting Linux, the board info and command line data 423 * have to be in the first 64 MB of memory, since this is 424 * the maximum mapped by the Linux kernel during initialization. 425 */ 426 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 427 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 428 429 #if defined(CONFIG_CMD_KGDB) 430 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 431 #endif 432 433 /* 434 * Environment Configuration 435 */ 436 437 /* The mac addresses for all ethernet interface */ 438 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 439 #define CONFIG_HAS_ETH0 440 #define CONFIG_HAS_ETH1 441 #define CONFIG_HAS_ETH2 442 #define CONFIG_HAS_ETH3 443 #endif 444 445 #define CONFIG_IPADDR 192.168.1.253 446 447 #define CONFIG_HOSTNAME unknown 448 #define CONFIG_ROOTPATH "/nfsroot" 449 #define CONFIG_BOOTFILE "your.uImage" 450 451 #define CONFIG_SERVERIP 192.168.1.1 452 #define CONFIG_GATEWAYIP 192.168.1.1 453 #define CONFIG_NETMASK 255.255.255.0 454 455 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 456 457 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 458 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 459 460 #define CONFIG_BAUDRATE 115200 461 462 #define CONFIG_EXTRA_ENV_SETTINGS \ 463 "netdev=eth0\0" \ 464 "consoledev=ttyS0\0" \ 465 "ramdiskaddr=600000\0" \ 466 "ramdiskfile=your.ramdisk.u-boot\0" \ 467 "fdtaddr=400000\0" \ 468 "fdtfile=your.fdt.dtb\0" \ 469 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 470 "nfsroot=$serverip:$rootpath " \ 471 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 472 "console=$consoledev,$baudrate $othbootargs\0" \ 473 "ramargs=setenv bootargs root=/dev/ram rw " \ 474 "console=$consoledev,$baudrate $othbootargs\0" \ 475 476 477 #define CONFIG_NFSBOOTCOMMAND \ 478 "run nfsargs;" \ 479 "tftp $loadaddr $bootfile;" \ 480 "tftp $fdtaddr $fdtfile;" \ 481 "bootm $loadaddr - $fdtaddr" 482 483 484 #define CONFIG_RAMBOOTCOMMAND \ 485 "run ramargs;" \ 486 "tftp $ramdiskaddr $ramdiskfile;" \ 487 "tftp $loadaddr $bootfile;" \ 488 "bootm $loadaddr $ramdiskaddr" 489 490 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 491 492 #endif /* __CONFIG_H */ 493