1 /* 2 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8568mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 17 #define CONFIG_SYS_TEXT_BASE 0xfff80000 18 19 #define CONFIG_SYS_SRIO 20 #define CONFIG_SRIO1 /* SRIO port 1 */ 21 22 #define CONFIG_PCI1 1 /* PCI controller */ 23 #define CONFIG_PCIE1 1 /* PCIE controller */ 24 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 25 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 26 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 27 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 28 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 29 #define CONFIG_QE /* Enable QE */ 30 #define CONFIG_ENV_OVERWRITE 31 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 32 33 #ifndef __ASSEMBLY__ 34 extern unsigned long get_clock_freq(void); 35 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 36 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 37 38 /* 39 * These can be toggled for performance analysis, otherwise use default. 40 */ 41 #define CONFIG_L2_CACHE /* toggle L2 cache */ 42 #define CONFIG_BTB /* toggle branch predition */ 43 44 /* 45 * Only possible on E500 Version 2 or newer cores. 46 */ 47 #define CONFIG_ENABLE_36BIT_PHYS 1 48 49 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 50 51 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 52 #define CONFIG_SYS_MEMTEST_END 0x00400000 53 54 #define CONFIG_SYS_CCSRBAR 0xe0000000 55 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 56 57 /* DDR Setup */ 58 #define CONFIG_SYS_FSL_DDR2 59 #undef CONFIG_FSL_DDR_INTERACTIVE 60 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 61 #define CONFIG_DDR_SPD 62 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 63 64 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 65 66 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 67 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 68 69 #define CONFIG_NUM_DDR_CONTROLLERS 1 70 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 71 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 72 73 /* I2C addresses of SPD EEPROMs */ 74 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 75 76 /* Make sure required options are set */ 77 #ifndef CONFIG_SPD_EEPROM 78 #error ("CONFIG_SPD_EEPROM is required") 79 #endif 80 81 #undef CONFIG_CLOCKS_IN_MHZ 82 83 /* 84 * Local Bus Definitions 85 */ 86 87 /* 88 * FLASH on the Local Bus 89 * Two banks, 8M each, using the CFI driver. 90 * Boot from BR0/OR0 bank at 0xff00_0000 91 * Alternate BR1/OR1 bank at 0xff80_0000 92 * 93 * BR0, BR1: 94 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 95 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 96 * Port Size = 16 bits = BRx[19:20] = 10 97 * Use GPCM = BRx[24:26] = 000 98 * Valid = BRx[31] = 1 99 * 100 * 0 4 8 12 16 20 24 28 101 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 102 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 103 * 104 * OR0, OR1: 105 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 106 * Reserved ORx[17:18] = 11, confusion here? 107 * CSNT = ORx[20] = 1 108 * ACS = half cycle delay = ORx[21:22] = 11 109 * SCY = 6 = ORx[24:27] = 0110 110 * TRLX = use relaxed timing = ORx[29] = 1 111 * EAD = use external address latch delay = OR[31] = 1 112 * 113 * 0 4 8 12 16 20 24 28 114 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 115 */ 116 #define CONFIG_SYS_BCSR_BASE 0xf8000000 117 118 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 119 120 /*Chip select 0 - Flash*/ 121 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 122 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 123 124 /*Chip slelect 1 - BCSR*/ 125 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 126 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 127 128 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 129 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 130 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 131 #undef CONFIG_SYS_FLASH_CHECKSUM 132 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 133 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 134 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 136 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_EMPTY_INFO 140 141 /* 142 * SDRAM on the LocalBus 143 */ 144 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 145 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 146 147 /*Chip select 2 - SDRAM*/ 148 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 149 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 150 151 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 152 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 153 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 154 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 155 156 /* 157 * Common settings for all Local Bus SDRAM commands. 158 * At run time, either BSMA1516 (for CPU 1.1) 159 * or BSMA1617 (for CPU 1.0) (old) 160 * is OR'ed in too. 161 */ 162 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 163 | LSDMR_PRETOACT7 \ 164 | LSDMR_ACTTORW7 \ 165 | LSDMR_BL8 \ 166 | LSDMR_WRC4 \ 167 | LSDMR_CL3 \ 168 | LSDMR_RFEN \ 169 ) 170 171 /* 172 * The bcsr registers are connected to CS3 on MDS. 173 * The new memory map places bcsr at 0xf8000000. 174 * 175 * For BR3, need: 176 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 177 * port-size = 8-bits = BR[19:20] = 01 178 * no parity checking = BR[21:22] = 00 179 * GPMC for MSEL = BR[24:26] = 000 180 * Valid = BR[31] = 1 181 * 182 * 0 4 8 12 16 20 24 28 183 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 184 * 185 * For OR3, need: 186 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 187 * disable buffer ctrl OR[19] = 0 188 * CSNT OR[20] = 1 189 * ACS OR[21:22] = 11 190 * XACS OR[23] = 1 191 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 192 * SETA OR[28] = 0 193 * TRLX OR[29] = 1 194 * EHTR OR[30] = 1 195 * EAD extra time OR[31] = 1 196 * 197 * 0 4 8 12 16 20 24 28 198 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 199 */ 200 #define CONFIG_SYS_BCSR (0xf8000000) 201 202 /*Chip slelect 4 - PIB*/ 203 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 204 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 205 206 /*Chip select 5 - PIB*/ 207 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 208 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 213 214 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 216 217 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 218 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 219 220 /* Serial Port */ 221 #define CONFIG_CONS_INDEX 1 222 #define CONFIG_SYS_NS16550_SERIAL 223 #define CONFIG_SYS_NS16550_REG_SIZE 1 224 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 225 226 #define CONFIG_SYS_BAUDRATE_TABLE \ 227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 228 229 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 230 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 231 232 /* 233 * I2C 234 */ 235 #define CONFIG_SYS_I2C 236 #define CONFIG_SYS_I2C_FSL 237 #define CONFIG_SYS_FSL_I2C_SPEED 400000 238 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 239 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 240 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 241 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 242 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 243 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 244 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 245 246 /* 247 * General PCI 248 * Memory Addresses are mapped 1-1. I/O is mapped from 0 249 */ 250 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 251 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 252 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 253 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 254 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 255 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 256 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 257 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 258 259 #define CONFIG_SYS_PCIE1_NAME "Slot" 260 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 261 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 262 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 263 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 264 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 265 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 266 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 267 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 268 269 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 270 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 271 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 272 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 273 274 #ifdef CONFIG_QE 275 /* 276 * QE UEC ethernet configuration 277 */ 278 #define CONFIG_UEC_ETH 279 #ifndef CONFIG_TSEC_ENET 280 #define CONFIG_ETHPRIME "UEC0" 281 #endif 282 #define CONFIG_PHY_MODE_NEED_CHANGE 283 #define CONFIG_eTSEC_MDIO_BUS 284 285 #ifdef CONFIG_eTSEC_MDIO_BUS 286 #define CONFIG_MIIM_ADDRESS 0xE0024520 287 #endif 288 289 #define CONFIG_UEC_ETH1 /* GETH1 */ 290 291 #ifdef CONFIG_UEC_ETH1 292 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 293 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 294 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 295 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 296 #define CONFIG_SYS_UEC1_PHY_ADDR 7 297 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 298 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 299 #endif 300 301 #define CONFIG_UEC_ETH2 /* GETH2 */ 302 303 #ifdef CONFIG_UEC_ETH2 304 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 305 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 306 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 307 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 308 #define CONFIG_SYS_UEC2_PHY_ADDR 1 309 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 310 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 311 #endif 312 #endif /* CONFIG_QE */ 313 314 #if defined(CONFIG_PCI) 315 #undef CONFIG_EEPRO100 316 #undef CONFIG_TULIP 317 318 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 319 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 320 321 #endif /* CONFIG_PCI */ 322 323 #if defined(CONFIG_TSEC_ENET) 324 325 #define CONFIG_MII 1 /* MII PHY management */ 326 #define CONFIG_TSEC1 1 327 #define CONFIG_TSEC1_NAME "eTSEC0" 328 #define CONFIG_TSEC2 1 329 #define CONFIG_TSEC2_NAME "eTSEC1" 330 331 #define TSEC1_PHY_ADDR 2 332 #define TSEC2_PHY_ADDR 3 333 334 #define TSEC1_PHYIDX 0 335 #define TSEC2_PHYIDX 0 336 337 #define TSEC1_FLAGS TSEC_GIGABIT 338 #define TSEC2_FLAGS TSEC_GIGABIT 339 340 /* Options are: eTSEC[0-1] */ 341 #define CONFIG_ETHPRIME "eTSEC0" 342 343 #endif /* CONFIG_TSEC_ENET */ 344 345 /* 346 * Environment 347 */ 348 #define CONFIG_ENV_IS_IN_FLASH 1 349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 350 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 351 #define CONFIG_ENV_SIZE 0x2000 352 353 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 354 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 355 356 /* 357 * BOOTP options 358 */ 359 #define CONFIG_BOOTP_BOOTFILESIZE 360 #define CONFIG_BOOTP_BOOTPATH 361 #define CONFIG_BOOTP_GATEWAY 362 #define CONFIG_BOOTP_HOSTNAME 363 364 /* 365 * Command line configuration. 366 */ 367 #define CONFIG_CMD_IRQ 368 #define CONFIG_CMD_REGINFO 369 370 #if defined(CONFIG_PCI) 371 #define CONFIG_CMD_PCI 372 #endif 373 374 #undef CONFIG_WATCHDOG /* watchdog disabled */ 375 376 /* 377 * Miscellaneous configurable options 378 */ 379 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 380 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 381 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 382 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 383 #if defined(CONFIG_CMD_KGDB) 384 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 385 #else 386 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 387 #endif 388 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 389 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 390 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 391 392 /* 393 * For booting Linux, the board info and command line data 394 * have to be in the first 64 MB of memory, since this is 395 * the maximum mapped by the Linux kernel during initialization. 396 */ 397 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 398 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 399 400 #if defined(CONFIG_CMD_KGDB) 401 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 402 #endif 403 404 /* 405 * Environment Configuration 406 */ 407 408 /* The mac addresses for all ethernet interface */ 409 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 410 #define CONFIG_HAS_ETH0 411 #define CONFIG_HAS_ETH1 412 #define CONFIG_HAS_ETH2 413 #define CONFIG_HAS_ETH3 414 #endif 415 416 #define CONFIG_IPADDR 192.168.1.253 417 418 #define CONFIG_HOSTNAME unknown 419 #define CONFIG_ROOTPATH "/nfsroot" 420 #define CONFIG_BOOTFILE "your.uImage" 421 422 #define CONFIG_SERVERIP 192.168.1.1 423 #define CONFIG_GATEWAYIP 192.168.1.1 424 #define CONFIG_NETMASK 255.255.255.0 425 426 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 427 428 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 429 430 #define CONFIG_BAUDRATE 115200 431 432 #define CONFIG_EXTRA_ENV_SETTINGS \ 433 "netdev=eth0\0" \ 434 "consoledev=ttyS0\0" \ 435 "ramdiskaddr=600000\0" \ 436 "ramdiskfile=your.ramdisk.u-boot\0" \ 437 "fdtaddr=400000\0" \ 438 "fdtfile=your.fdt.dtb\0" \ 439 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 440 "nfsroot=$serverip:$rootpath " \ 441 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 442 "console=$consoledev,$baudrate $othbootargs\0" \ 443 "ramargs=setenv bootargs root=/dev/ram rw " \ 444 "console=$consoledev,$baudrate $othbootargs\0" \ 445 446 #define CONFIG_NFSBOOTCOMMAND \ 447 "run nfsargs;" \ 448 "tftp $loadaddr $bootfile;" \ 449 "tftp $fdtaddr $fdtfile;" \ 450 "bootm $loadaddr - $fdtaddr" 451 452 #define CONFIG_RAMBOOTCOMMAND \ 453 "run ramargs;" \ 454 "tftp $ramdiskaddr $ramdiskfile;" \ 455 "tftp $loadaddr $bootfile;" \ 456 "bootm $loadaddr $ramdiskaddr" 457 458 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 459 460 #endif /* __CONFIG_H */ 461