1 /* 2 * Copyright 2004-2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 37 #define CONFIG_PCI1 1 /* PCI controller */ 38 #define CONFIG_PCIE1 1 /* PCIE controller */ 39 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 41 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 42 #define CONFIG_QE /* Enable QE */ 43 #define CONFIG_ENV_OVERWRITE 44 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 45 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 46 /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ 47 48 /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ 49 /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ 50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 51 52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 53 54 /* 55 * When initializing flash, if we cannot find the manufacturer ID, 56 * assume this is the AMD flash associated with the MDS board. 57 * This allows booting from a promjet. 58 */ 59 #define CONFIG_ASSUME_AMD_FLASH 60 61 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 62 63 #ifndef __ASSEMBLY__ 64 extern unsigned long get_clock_freq(void); 65 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 66 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 67 68 /* 69 * These can be toggled for performance analysis, otherwise use default. 70 */ 71 #define CONFIG_L2_CACHE /* toggle L2 cache */ 72 #define CONFIG_BTB /* toggle branch predition */ 73 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 74 75 /* 76 * Only possible on E500 Version 2 or newer cores. 77 */ 78 #define CONFIG_ENABLE_36BIT_PHYS 1 79 80 81 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 82 83 #undef CFG_DRAM_TEST /* memory test, takes time */ 84 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 85 #define CFG_MEMTEST_END 0x00400000 86 87 /* 88 * Base addresses -- Note these are effective addresses where the 89 * actual resources get mapped (not physical addresses) 90 */ 91 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 92 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 93 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 94 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 95 96 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 97 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 98 99 /* 100 * DDR Setup 101 */ 102 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 103 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 104 105 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 106 107 /* 108 * Make sure required options are set 109 */ 110 #ifndef CONFIG_SPD_EEPROM 111 #error ("CONFIG_SPD_EEPROM is required") 112 #endif 113 114 #undef CONFIG_CLOCKS_IN_MHZ 115 116 117 /* 118 * Local Bus Definitions 119 */ 120 121 /* 122 * FLASH on the Local Bus 123 * Two banks, 8M each, using the CFI driver. 124 * Boot from BR0/OR0 bank at 0xff00_0000 125 * Alternate BR1/OR1 bank at 0xff80_0000 126 * 127 * BR0, BR1: 128 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 129 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 130 * Port Size = 16 bits = BRx[19:20] = 10 131 * Use GPCM = BRx[24:26] = 000 132 * Valid = BRx[31] = 1 133 * 134 * 0 4 8 12 16 20 24 28 135 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 136 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 137 * 138 * OR0, OR1: 139 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 140 * Reserved ORx[17:18] = 11, confusion here? 141 * CSNT = ORx[20] = 1 142 * ACS = half cycle delay = ORx[21:22] = 11 143 * SCY = 6 = ORx[24:27] = 0110 144 * TRLX = use relaxed timing = ORx[29] = 1 145 * EAD = use external address latch delay = OR[31] = 1 146 * 147 * 0 4 8 12 16 20 24 28 148 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 149 */ 150 #define CFG_BCSR_BASE 0xf8000000 151 152 #define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 153 154 /*Chip select 0 - Flash*/ 155 #define CFG_BR0_PRELIM 0xfe001001 156 #define CFG_OR0_PRELIM 0xfe006ff7 157 158 /*Chip slelect 1 - BCSR*/ 159 #define CFG_BR1_PRELIM 0xf8000801 160 #define CFG_OR1_PRELIM 0xffffe9f7 161 162 /*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */ 163 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 164 #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ 165 #undef CFG_FLASH_CHECKSUM 166 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 167 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 168 169 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 170 171 #define CFG_FLASH_CFI_DRIVER 172 #define CFG_FLASH_CFI 173 #define CFG_FLASH_EMPTY_INFO 174 175 176 /* 177 * SDRAM on the LocalBus 178 */ 179 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 180 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 181 182 183 /*Chip select 2 - SDRAM*/ 184 #define CFG_BR2_PRELIM 0xf0001861 185 #define CFG_OR2_PRELIM 0xfc006901 186 187 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 188 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 189 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 190 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 191 192 /* 193 * LSDMR masks 194 */ 195 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 196 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 197 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 198 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 199 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 200 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 201 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 202 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 203 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 204 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 205 206 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 207 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 208 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 209 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 210 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 211 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 212 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 213 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 214 215 /* 216 * Common settings for all Local Bus SDRAM commands. 217 * At run time, either BSMA1516 (for CPU 1.1) 218 * or BSMA1617 (for CPU 1.0) (old) 219 * is OR'ed in too. 220 */ 221 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 222 | CFG_LBC_LSDMR_PRETOACT7 \ 223 | CFG_LBC_LSDMR_ACTTORW7 \ 224 | CFG_LBC_LSDMR_BL8 \ 225 | CFG_LBC_LSDMR_WRC4 \ 226 | CFG_LBC_LSDMR_CL3 \ 227 | CFG_LBC_LSDMR_RFEN \ 228 ) 229 230 /* 231 * The bcsr registers are connected to CS3 on MDS. 232 * The new memory map places bcsr at 0xf8000000. 233 * 234 * For BR3, need: 235 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 236 * port-size = 8-bits = BR[19:20] = 01 237 * no parity checking = BR[21:22] = 00 238 * GPMC for MSEL = BR[24:26] = 000 239 * Valid = BR[31] = 1 240 * 241 * 0 4 8 12 16 20 24 28 242 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 243 * 244 * For OR3, need: 245 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 246 * disable buffer ctrl OR[19] = 0 247 * CSNT OR[20] = 1 248 * ACS OR[21:22] = 11 249 * XACS OR[23] = 1 250 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 251 * SETA OR[28] = 0 252 * TRLX OR[29] = 1 253 * EHTR OR[30] = 1 254 * EAD extra time OR[31] = 1 255 * 256 * 0 4 8 12 16 20 24 28 257 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 258 */ 259 #define CFG_BCSR (0xf8000000) 260 261 /*Chip slelect 4 - PIB*/ 262 #define CFG_BR4_PRELIM 0xf8008801 263 #define CFG_OR4_PRELIM 0xffffe9f7 264 265 /*Chip select 5 - PIB*/ 266 #define CFG_BR5_PRELIM 0xf8010801 267 #define CFG_OR5_PRELIM 0xffff69f7 268 269 #define CONFIG_L1_INIT_RAM 270 #define CFG_INIT_RAM_LOCK 1 271 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 272 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 273 274 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 275 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 276 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 277 278 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 279 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 280 281 /* Serial Port */ 282 #define CONFIG_CONS_INDEX 1 283 #undef CONFIG_SERIAL_SOFTWARE_FIFO 284 #define CFG_NS16550 285 #define CFG_NS16550_SERIAL 286 #define CFG_NS16550_REG_SIZE 1 287 #define CFG_NS16550_CLK get_bus_freq(0) 288 289 #define CFG_BAUDRATE_TABLE \ 290 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 291 292 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 293 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 294 295 /* Use the HUSH parser*/ 296 #define CFG_HUSH_PARSER 297 #ifdef CFG_HUSH_PARSER 298 #define CFG_PROMPT_HUSH_PS2 "> " 299 #endif 300 301 /* pass open firmware flat tree */ 302 #define CONFIG_OF_LIBFDT 1 303 #define CONFIG_OF_BOARD_SETUP 1 304 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 305 306 /* 307 * I2C 308 */ 309 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 310 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 311 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 312 #define CONFIG_I2C_MULTI_BUS 313 #define CONFIG_I2C_CMD_TREE 314 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 315 #define CFG_I2C_EEPROM_ADDR 0x52 316 #define CFG_I2C_SLAVE 0x7F 317 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 318 #define CFG_I2C_OFFSET 0x3000 319 #define CFG_I2C2_OFFSET 0x3100 320 321 /* 322 * General PCI 323 * Memory Addresses are mapped 1-1. I/O is mapped from 0 324 */ 325 #define CFG_PCI1_MEM_BASE 0x80000000 326 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 327 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 328 #define CFG_PCI1_IO_BASE 0x00000000 329 #define CFG_PCI1_IO_PHYS 0xe2000000 330 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ 331 332 #define CFG_PCIE1_MEM_BASE 0xa0000000 333 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 334 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 335 #define CFG_PCIE1_IO_BASE 0x00000000 336 #define CFG_PCIE1_IO_PHYS 0xe2800000 337 #define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */ 338 339 #define CFG_SRIO_MEM_BASE 0xc0000000 340 341 #ifdef CONFIG_QE 342 /* 343 * QE UEC ethernet configuration 344 */ 345 #define CONFIG_UEC_ETH 346 #ifndef CONFIG_TSEC_ENET 347 #define CONFIG_ETHPRIME "FSL UEC0" 348 #endif 349 #define CONFIG_PHY_MODE_NEED_CHANGE 350 #define CONFIG_eTSEC_MDIO_BUS 351 352 #ifdef CONFIG_eTSEC_MDIO_BUS 353 #define CONFIG_MIIM_ADDRESS 0xE0024520 354 #endif 355 356 #define CONFIG_UEC_ETH1 /* GETH1 */ 357 358 #ifdef CONFIG_UEC_ETH1 359 #define CFG_UEC1_UCC_NUM 0 /* UCC1 */ 360 #define CFG_UEC1_RX_CLK QE_CLK_NONE 361 #define CFG_UEC1_TX_CLK QE_CLK16 362 #define CFG_UEC1_ETH_TYPE GIGA_ETH 363 #define CFG_UEC1_PHY_ADDR 7 364 #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII 365 #endif 366 367 #define CONFIG_UEC_ETH2 /* GETH2 */ 368 369 #ifdef CONFIG_UEC_ETH2 370 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ 371 #define CFG_UEC2_RX_CLK QE_CLK_NONE 372 #define CFG_UEC2_TX_CLK QE_CLK16 373 #define CFG_UEC2_ETH_TYPE GIGA_ETH 374 #define CFG_UEC2_PHY_ADDR 1 375 #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII 376 #endif 377 #endif /* CONFIG_QE */ 378 379 #if defined(CONFIG_PCI) 380 381 #define CONFIG_NET_MULTI 382 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 383 384 #undef CONFIG_EEPRO100 385 #undef CONFIG_TULIP 386 387 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 388 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 389 390 /* PCI view of System Memory */ 391 #define CFG_PCI_MEMORY_BUS 0x00000000 392 #define CFG_PCI_MEMORY_PHYS 0x00000000 393 #define CFG_PCI_MEMORY_SIZE 0x80000000 394 395 #endif /* CONFIG_PCI */ 396 397 #ifndef CONFIG_NET_MULTI 398 #define CONFIG_NET_MULTI 1 399 #endif 400 401 #if defined(CONFIG_TSEC_ENET) 402 403 #define CONFIG_MII 1 /* MII PHY management */ 404 #define CONFIG_TSEC1 1 405 #define CONFIG_TSEC1_NAME "eTSEC0" 406 #define CONFIG_TSEC2 1 407 #define CONFIG_TSEC2_NAME "eTSEC1" 408 409 #define TSEC1_PHY_ADDR 2 410 #define TSEC2_PHY_ADDR 3 411 412 #define TSEC1_PHYIDX 0 413 #define TSEC2_PHYIDX 0 414 415 #define TSEC1_FLAGS TSEC_GIGABIT 416 #define TSEC2_FLAGS TSEC_GIGABIT 417 418 /* Options are: eTSEC[0-1] */ 419 #define CONFIG_ETHPRIME "eTSEC0" 420 421 #endif /* CONFIG_TSEC_ENET */ 422 423 /* 424 * Environment 425 */ 426 #define CFG_ENV_IS_IN_FLASH 1 427 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 428 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 429 #define CFG_ENV_SIZE 0x2000 430 431 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 432 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 433 434 435 /* 436 * BOOTP options 437 */ 438 #define CONFIG_BOOTP_BOOTFILESIZE 439 #define CONFIG_BOOTP_BOOTPATH 440 #define CONFIG_BOOTP_GATEWAY 441 #define CONFIG_BOOTP_HOSTNAME 442 443 444 /* 445 * Command line configuration. 446 */ 447 #include <config_cmd_default.h> 448 449 #define CONFIG_CMD_PING 450 #define CONFIG_CMD_I2C 451 #define CONFIG_CMD_MII 452 #define CONFIG_CMD_ELF 453 454 #if defined(CONFIG_PCI) 455 #define CONFIG_CMD_PCI 456 #endif 457 458 459 #undef CONFIG_WATCHDOG /* watchdog disabled */ 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CFG_LONGHELP /* undef to save memory */ 465 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 466 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 467 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 468 #if defined(CONFIG_CMD_KGDB) 469 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 470 #else 471 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 472 #endif 473 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 474 #define CFG_MAXARGS 16 /* max number of command args */ 475 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 476 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 477 478 /* 479 * For booting Linux, the board info and command line data 480 * have to be in the first 8 MB of memory, since this is 481 * the maximum mapped by the Linux kernel during initialization. 482 */ 483 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 484 485 /* 486 * Internal Definitions 487 * 488 * Boot Flags 489 */ 490 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 491 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 492 493 #if defined(CONFIG_CMD_KGDB) 494 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 495 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 496 #endif 497 498 /* 499 * Environment Configuration 500 */ 501 502 /* The mac addresses for all ethernet interface */ 503 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 504 #define CONFIG_HAS_ETH0 505 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 506 #define CONFIG_HAS_ETH1 507 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 508 #define CONFIG_HAS_ETH2 509 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 510 #define CONFIG_HAS_ETH3 511 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 512 #endif 513 514 #define CONFIG_IPADDR 192.168.1.253 515 516 #define CONFIG_HOSTNAME unknown 517 #define CONFIG_ROOTPATH /nfsroot 518 #define CONFIG_BOOTFILE your.uImage 519 520 #define CONFIG_SERVERIP 192.168.1.1 521 #define CONFIG_GATEWAYIP 192.168.1.1 522 #define CONFIG_NETMASK 255.255.255.0 523 524 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 525 526 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 527 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 528 529 #define CONFIG_BAUDRATE 115200 530 531 #define CONFIG_EXTRA_ENV_SETTINGS \ 532 "netdev=eth0\0" \ 533 "consoledev=ttyS0\0" \ 534 "ramdiskaddr=600000\0" \ 535 "ramdiskfile=your.ramdisk.u-boot\0" \ 536 "fdtaddr=400000\0" \ 537 "fdtfile=your.fdt.dtb\0" \ 538 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 539 "nfsroot=$serverip:$rootpath " \ 540 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 541 "console=$consoledev,$baudrate $othbootargs\0" \ 542 "ramargs=setenv bootargs root=/dev/ram rw " \ 543 "console=$consoledev,$baudrate $othbootargs\0" \ 544 545 546 #define CONFIG_NFSBOOTCOMMAND \ 547 "run nfsargs;" \ 548 "tftp $loadaddr $bootfile;" \ 549 "tftp $fdtaddr $fdtfile;" \ 550 "bootm $loadaddr - $fdtaddr" 551 552 553 #define CONFIG_RAMBOOTCOMMAND \ 554 "run ramargs;" \ 555 "tftp $ramdiskaddr $ramdiskfile;" \ 556 "tftp $loadaddr $bootfile;" \ 557 "bootm $loadaddr $ramdiskaddr" 558 559 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 560 561 #endif /* __CONFIG_H */ 562