1 /* 2 * Copyright 2004-2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 37 #define CONFIG_PCI1 1 /* PCI controller */ 38 #define CONFIG_PCIE1 1 /* PCIE controller */ 39 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 41 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 42 #define CONFIG_QE /* Enable QE */ 43 #define CONFIG_ENV_OVERWRITE 44 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 45 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 46 /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ 47 48 /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ 49 /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ 50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 51 52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 53 54 /* 55 * When initializing flash, if we cannot find the manufacturer ID, 56 * assume this is the AMD flash associated with the MDS board. 57 * This allows booting from a promjet. 58 */ 59 #define CONFIG_ASSUME_AMD_FLASH 60 61 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 62 63 #ifndef __ASSEMBLY__ 64 extern unsigned long get_clock_freq(void); 65 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 66 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 67 68 /* 69 * These can be toggled for performance analysis, otherwise use default. 70 */ 71 #define CONFIG_L2_CACHE /* toggle L2 cache */ 72 #define CONFIG_BTB /* toggle branch predition */ 73 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 74 75 /* 76 * Only possible on E500 Version 2 or newer cores. 77 */ 78 #define CONFIG_ENABLE_36BIT_PHYS 1 79 80 81 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 82 83 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 84 #define CFG_MEMTEST_END 0x00400000 85 86 /* 87 * Base addresses -- Note these are effective addresses where the 88 * actual resources get mapped (not physical addresses) 89 */ 90 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 91 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 92 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 93 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 94 95 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 96 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 97 98 /* 99 * DDR Setup 100 */ 101 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 102 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 103 104 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 105 106 /* 107 * Make sure required options are set 108 */ 109 #ifndef CONFIG_SPD_EEPROM 110 #error ("CONFIG_SPD_EEPROM is required") 111 #endif 112 113 #undef CONFIG_CLOCKS_IN_MHZ 114 115 116 /* 117 * Local Bus Definitions 118 */ 119 120 /* 121 * FLASH on the Local Bus 122 * Two banks, 8M each, using the CFI driver. 123 * Boot from BR0/OR0 bank at 0xff00_0000 124 * Alternate BR1/OR1 bank at 0xff80_0000 125 * 126 * BR0, BR1: 127 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 128 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 129 * Port Size = 16 bits = BRx[19:20] = 10 130 * Use GPCM = BRx[24:26] = 000 131 * Valid = BRx[31] = 1 132 * 133 * 0 4 8 12 16 20 24 28 134 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 135 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 136 * 137 * OR0, OR1: 138 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 139 * Reserved ORx[17:18] = 11, confusion here? 140 * CSNT = ORx[20] = 1 141 * ACS = half cycle delay = ORx[21:22] = 11 142 * SCY = 6 = ORx[24:27] = 0110 143 * TRLX = use relaxed timing = ORx[29] = 1 144 * EAD = use external address latch delay = OR[31] = 1 145 * 146 * 0 4 8 12 16 20 24 28 147 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 148 */ 149 #define CFG_BCSR_BASE 0xf8000000 150 151 #define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 152 153 /*Chip select 0 - Flash*/ 154 #define CFG_BR0_PRELIM 0xfe001001 155 #define CFG_OR0_PRELIM 0xfe006ff7 156 157 /*Chip slelect 1 - BCSR*/ 158 #define CFG_BR1_PRELIM 0xf8000801 159 #define CFG_OR1_PRELIM 0xffffe9f7 160 161 /*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */ 162 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 163 #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ 164 #undef CFG_FLASH_CHECKSUM 165 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 166 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 167 168 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 169 170 #define CFG_FLASH_CFI_DRIVER 171 #define CFG_FLASH_CFI 172 #define CFG_FLASH_EMPTY_INFO 173 174 175 /* 176 * SDRAM on the LocalBus 177 */ 178 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 179 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 180 181 182 /*Chip select 2 - SDRAM*/ 183 #define CFG_BR2_PRELIM 0xf0001861 184 #define CFG_OR2_PRELIM 0xfc006901 185 186 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 187 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 188 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 189 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 190 191 /* 192 * LSDMR masks 193 */ 194 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 195 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 196 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 197 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 198 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 199 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 200 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 201 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 202 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 203 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 204 205 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 206 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 207 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 208 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 209 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 210 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 211 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 212 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 213 214 /* 215 * Common settings for all Local Bus SDRAM commands. 216 * At run time, either BSMA1516 (for CPU 1.1) 217 * or BSMA1617 (for CPU 1.0) (old) 218 * is OR'ed in too. 219 */ 220 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 221 | CFG_LBC_LSDMR_PRETOACT7 \ 222 | CFG_LBC_LSDMR_ACTTORW7 \ 223 | CFG_LBC_LSDMR_BL8 \ 224 | CFG_LBC_LSDMR_WRC4 \ 225 | CFG_LBC_LSDMR_CL3 \ 226 | CFG_LBC_LSDMR_RFEN \ 227 ) 228 229 /* 230 * The bcsr registers are connected to CS3 on MDS. 231 * The new memory map places bcsr at 0xf8000000. 232 * 233 * For BR3, need: 234 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 235 * port-size = 8-bits = BR[19:20] = 01 236 * no parity checking = BR[21:22] = 00 237 * GPMC for MSEL = BR[24:26] = 000 238 * Valid = BR[31] = 1 239 * 240 * 0 4 8 12 16 20 24 28 241 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 242 * 243 * For OR3, need: 244 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 245 * disable buffer ctrl OR[19] = 0 246 * CSNT OR[20] = 1 247 * ACS OR[21:22] = 11 248 * XACS OR[23] = 1 249 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 250 * SETA OR[28] = 0 251 * TRLX OR[29] = 1 252 * EHTR OR[30] = 1 253 * EAD extra time OR[31] = 1 254 * 255 * 0 4 8 12 16 20 24 28 256 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 257 */ 258 #define CFG_BCSR (0xf8000000) 259 260 /*Chip slelect 4 - PIB*/ 261 #define CFG_BR4_PRELIM 0xf8008801 262 #define CFG_OR4_PRELIM 0xffffe9f7 263 264 /*Chip select 5 - PIB*/ 265 #define CFG_BR5_PRELIM 0xf8010801 266 #define CFG_OR5_PRELIM 0xffff69f7 267 268 #define CONFIG_L1_INIT_RAM 269 #define CFG_INIT_RAM_LOCK 1 270 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 271 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 272 273 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 274 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 275 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 276 277 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 278 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 279 280 /* Serial Port */ 281 #define CONFIG_CONS_INDEX 1 282 #undef CONFIG_SERIAL_SOFTWARE_FIFO 283 #define CFG_NS16550 284 #define CFG_NS16550_SERIAL 285 #define CFG_NS16550_REG_SIZE 1 286 #define CFG_NS16550_CLK get_bus_freq(0) 287 288 #define CFG_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 290 291 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 292 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 293 294 /* Use the HUSH parser*/ 295 #define CFG_HUSH_PARSER 296 #ifdef CFG_HUSH_PARSER 297 #define CFG_PROMPT_HUSH_PS2 "> " 298 #endif 299 300 /* pass open firmware flat tree */ 301 #define CONFIG_OF_LIBFDT 1 302 #define CONFIG_OF_BOARD_SETUP 1 303 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 304 305 /* 306 * I2C 307 */ 308 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 309 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 310 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 311 #define CONFIG_I2C_MULTI_BUS 312 #define CONFIG_I2C_CMD_TREE 313 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 314 #define CFG_I2C_EEPROM_ADDR 0x52 315 #define CFG_I2C_SLAVE 0x7F 316 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 317 #define CFG_I2C_OFFSET 0x3000 318 #define CFG_I2C2_OFFSET 0x3100 319 320 /* 321 * General PCI 322 * Memory Addresses are mapped 1-1. I/O is mapped from 0 323 */ 324 #define CFG_PCI1_MEM_BASE 0x80000000 325 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 326 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 327 #define CFG_PCI1_IO_BASE 0x00000000 328 #define CFG_PCI1_IO_PHYS 0xe2000000 329 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ 330 331 #define CFG_PCIE1_MEM_BASE 0xa0000000 332 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 333 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 334 #define CFG_PCIE1_IO_BASE 0x00000000 335 #define CFG_PCIE1_IO_PHYS 0xe2800000 336 #define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */ 337 338 #define CFG_SRIO_MEM_BASE 0xc0000000 339 340 #ifdef CONFIG_QE 341 /* 342 * QE UEC ethernet configuration 343 */ 344 #define CONFIG_UEC_ETH 345 #ifndef CONFIG_TSEC_ENET 346 #define CONFIG_ETHPRIME "FSL UEC0" 347 #endif 348 #define CONFIG_PHY_MODE_NEED_CHANGE 349 #define CONFIG_eTSEC_MDIO_BUS 350 351 #ifdef CONFIG_eTSEC_MDIO_BUS 352 #define CONFIG_MIIM_ADDRESS 0xE0024520 353 #endif 354 355 #define CONFIG_UEC_ETH1 /* GETH1 */ 356 357 #ifdef CONFIG_UEC_ETH1 358 #define CFG_UEC1_UCC_NUM 0 /* UCC1 */ 359 #define CFG_UEC1_RX_CLK QE_CLK_NONE 360 #define CFG_UEC1_TX_CLK QE_CLK16 361 #define CFG_UEC1_ETH_TYPE GIGA_ETH 362 #define CFG_UEC1_PHY_ADDR 7 363 #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII 364 #endif 365 366 #define CONFIG_UEC_ETH2 /* GETH2 */ 367 368 #ifdef CONFIG_UEC_ETH2 369 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ 370 #define CFG_UEC2_RX_CLK QE_CLK_NONE 371 #define CFG_UEC2_TX_CLK QE_CLK16 372 #define CFG_UEC2_ETH_TYPE GIGA_ETH 373 #define CFG_UEC2_PHY_ADDR 1 374 #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII 375 #endif 376 #endif /* CONFIG_QE */ 377 378 #if defined(CONFIG_PCI) 379 380 #define CONFIG_NET_MULTI 381 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 382 383 #undef CONFIG_EEPRO100 384 #undef CONFIG_TULIP 385 386 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 387 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 388 389 /* PCI view of System Memory */ 390 #define CFG_PCI_MEMORY_BUS 0x00000000 391 #define CFG_PCI_MEMORY_PHYS 0x00000000 392 #define CFG_PCI_MEMORY_SIZE 0x80000000 393 394 #endif /* CONFIG_PCI */ 395 396 #ifndef CONFIG_NET_MULTI 397 #define CONFIG_NET_MULTI 1 398 #endif 399 400 #if defined(CONFIG_TSEC_ENET) 401 402 #define CONFIG_MII 1 /* MII PHY management */ 403 #define CONFIG_TSEC1 1 404 #define CONFIG_TSEC1_NAME "eTSEC0" 405 #define CONFIG_TSEC2 1 406 #define CONFIG_TSEC2_NAME "eTSEC1" 407 408 #define TSEC1_PHY_ADDR 2 409 #define TSEC2_PHY_ADDR 3 410 411 #define TSEC1_PHYIDX 0 412 #define TSEC2_PHYIDX 0 413 414 #define TSEC1_FLAGS TSEC_GIGABIT 415 #define TSEC2_FLAGS TSEC_GIGABIT 416 417 /* Options are: eTSEC[0-1] */ 418 #define CONFIG_ETHPRIME "eTSEC0" 419 420 #endif /* CONFIG_TSEC_ENET */ 421 422 /* 423 * Environment 424 */ 425 #define CFG_ENV_IS_IN_FLASH 1 426 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 427 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 428 #define CFG_ENV_SIZE 0x2000 429 430 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 431 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 432 433 434 /* 435 * BOOTP options 436 */ 437 #define CONFIG_BOOTP_BOOTFILESIZE 438 #define CONFIG_BOOTP_BOOTPATH 439 #define CONFIG_BOOTP_GATEWAY 440 #define CONFIG_BOOTP_HOSTNAME 441 442 443 /* 444 * Command line configuration. 445 */ 446 #include <config_cmd_default.h> 447 448 #define CONFIG_CMD_PING 449 #define CONFIG_CMD_I2C 450 #define CONFIG_CMD_MII 451 #define CONFIG_CMD_ELF 452 453 #if defined(CONFIG_PCI) 454 #define CONFIG_CMD_PCI 455 #endif 456 457 458 #undef CONFIG_WATCHDOG /* watchdog disabled */ 459 460 /* 461 * Miscellaneous configurable options 462 */ 463 #define CFG_LONGHELP /* undef to save memory */ 464 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 465 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 466 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 467 #if defined(CONFIG_CMD_KGDB) 468 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 469 #else 470 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 471 #endif 472 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 473 #define CFG_MAXARGS 16 /* max number of command args */ 474 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 475 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 476 477 /* 478 * For booting Linux, the board info and command line data 479 * have to be in the first 8 MB of memory, since this is 480 * the maximum mapped by the Linux kernel during initialization. 481 */ 482 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 483 484 /* 485 * Internal Definitions 486 * 487 * Boot Flags 488 */ 489 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 490 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 491 492 #if defined(CONFIG_CMD_KGDB) 493 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 494 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 495 #endif 496 497 /* 498 * Environment Configuration 499 */ 500 501 /* The mac addresses for all ethernet interface */ 502 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 503 #define CONFIG_HAS_ETH0 504 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 505 #define CONFIG_HAS_ETH1 506 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 507 #define CONFIG_HAS_ETH2 508 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 509 #define CONFIG_HAS_ETH3 510 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 511 #endif 512 513 #define CONFIG_IPADDR 192.168.1.253 514 515 #define CONFIG_HOSTNAME unknown 516 #define CONFIG_ROOTPATH /nfsroot 517 #define CONFIG_BOOTFILE your.uImage 518 519 #define CONFIG_SERVERIP 192.168.1.1 520 #define CONFIG_GATEWAYIP 192.168.1.1 521 #define CONFIG_NETMASK 255.255.255.0 522 523 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 524 525 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 526 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 527 528 #define CONFIG_BAUDRATE 115200 529 530 #define CONFIG_EXTRA_ENV_SETTINGS \ 531 "netdev=eth0\0" \ 532 "consoledev=ttyS0\0" \ 533 "ramdiskaddr=600000\0" \ 534 "ramdiskfile=your.ramdisk.u-boot\0" \ 535 "fdtaddr=400000\0" \ 536 "fdtfile=your.fdt.dtb\0" \ 537 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 538 "nfsroot=$serverip:$rootpath " \ 539 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 540 "console=$consoledev,$baudrate $othbootargs\0" \ 541 "ramargs=setenv bootargs root=/dev/ram rw " \ 542 "console=$consoledev,$baudrate $othbootargs\0" \ 543 544 545 #define CONFIG_NFSBOOTCOMMAND \ 546 "run nfsargs;" \ 547 "tftp $loadaddr $bootfile;" \ 548 "tftp $fdtaddr $fdtfile;" \ 549 "bootm $loadaddr - $fdtaddr" 550 551 552 #define CONFIG_RAMBOOTCOMMAND \ 553 "run ramargs;" \ 554 "tftp $ramdiskaddr $ramdiskfile;" \ 555 "tftp $loadaddr $bootfile;" \ 556 "bootm $loadaddr $ramdiskaddr" 557 558 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 559 560 #endif /* __CONFIG_H */ 561