1 /* 2 * Copyright 2004-2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 37 #define CONFIG_PCI1 1 /* PCI controller */ 38 #define CONFIG_PCIE1 1 /* PCIE controller */ 39 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 42 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 /* 48 * When initializing flash, if we cannot find the manufacturer ID, 49 * assume this is the AMD flash associated with the MDS board. 50 * This allows booting from a promjet. 51 */ 52 #define CONFIG_ASSUME_AMD_FLASH 53 54 #ifndef __ASSEMBLY__ 55 extern unsigned long get_clock_freq(void); 56 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 57 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE /* toggle L2 cache */ 63 #define CONFIG_BTB /* toggle branch predition */ 64 65 /* 66 * Only possible on E500 Version 2 or newer cores. 67 */ 68 #define CONFIG_ENABLE_36BIT_PHYS 1 69 70 71 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 72 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 74 #define CONFIG_SYS_MEMTEST_END 0x00400000 75 76 /* 77 * Base addresses -- Note these are effective addresses where the 78 * actual resources get mapped (not physical addresses) 79 */ 80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 81 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 82 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 83 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 84 85 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 86 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 87 88 /* DDR Setup */ 89 #define CONFIG_FSL_DDR2 90 #undef CONFIG_FSL_DDR_INTERACTIVE 91 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 92 #define CONFIG_DDR_SPD 93 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 94 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 95 96 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 97 98 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 99 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 100 101 #define CONFIG_NUM_DDR_CONTROLLERS 1 102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 103 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 104 105 /* I2C addresses of SPD EEPROMs */ 106 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 107 108 /* Make sure required options are set */ 109 #ifndef CONFIG_SPD_EEPROM 110 #error ("CONFIG_SPD_EEPROM is required") 111 #endif 112 113 #undef CONFIG_CLOCKS_IN_MHZ 114 115 /* 116 * Local Bus Definitions 117 */ 118 119 /* 120 * FLASH on the Local Bus 121 * Two banks, 8M each, using the CFI driver. 122 * Boot from BR0/OR0 bank at 0xff00_0000 123 * Alternate BR1/OR1 bank at 0xff80_0000 124 * 125 * BR0, BR1: 126 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 127 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 128 * Port Size = 16 bits = BRx[19:20] = 10 129 * Use GPCM = BRx[24:26] = 000 130 * Valid = BRx[31] = 1 131 * 132 * 0 4 8 12 16 20 24 28 133 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 134 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 135 * 136 * OR0, OR1: 137 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 138 * Reserved ORx[17:18] = 11, confusion here? 139 * CSNT = ORx[20] = 1 140 * ACS = half cycle delay = ORx[21:22] = 11 141 * SCY = 6 = ORx[24:27] = 0110 142 * TRLX = use relaxed timing = ORx[29] = 1 143 * EAD = use external address latch delay = OR[31] = 1 144 * 145 * 0 4 8 12 16 20 24 28 146 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 147 */ 148 #define CONFIG_SYS_BCSR_BASE 0xf8000000 149 150 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 151 152 /*Chip select 0 - Flash*/ 153 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 154 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 155 156 /*Chip slelect 1 - BCSR*/ 157 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 158 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 159 160 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 162 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 163 #undef CONFIG_SYS_FLASH_CHECKSUM 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 167 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 168 169 #define CONFIG_FLASH_CFI_DRIVER 170 #define CONFIG_SYS_FLASH_CFI 171 #define CONFIG_SYS_FLASH_EMPTY_INFO 172 173 174 /* 175 * SDRAM on the LocalBus 176 */ 177 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 178 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 179 180 181 /*Chip select 2 - SDRAM*/ 182 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 183 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 184 185 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 186 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 187 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 188 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 189 190 /* 191 * Common settings for all Local Bus SDRAM commands. 192 * At run time, either BSMA1516 (for CPU 1.1) 193 * or BSMA1617 (for CPU 1.0) (old) 194 * is OR'ed in too. 195 */ 196 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 197 | LSDMR_PRETOACT7 \ 198 | LSDMR_ACTTORW7 \ 199 | LSDMR_BL8 \ 200 | LSDMR_WRC4 \ 201 | LSDMR_CL3 \ 202 | LSDMR_RFEN \ 203 ) 204 205 /* 206 * The bcsr registers are connected to CS3 on MDS. 207 * The new memory map places bcsr at 0xf8000000. 208 * 209 * For BR3, need: 210 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 211 * port-size = 8-bits = BR[19:20] = 01 212 * no parity checking = BR[21:22] = 00 213 * GPMC for MSEL = BR[24:26] = 000 214 * Valid = BR[31] = 1 215 * 216 * 0 4 8 12 16 20 24 28 217 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 218 * 219 * For OR3, need: 220 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 221 * disable buffer ctrl OR[19] = 0 222 * CSNT OR[20] = 1 223 * ACS OR[21:22] = 11 224 * XACS OR[23] = 1 225 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 226 * SETA OR[28] = 0 227 * TRLX OR[29] = 1 228 * EHTR OR[30] = 1 229 * EAD extra time OR[31] = 1 230 * 231 * 0 4 8 12 16 20 24 28 232 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 233 */ 234 #define CONFIG_SYS_BCSR (0xf8000000) 235 236 /*Chip slelect 4 - PIB*/ 237 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 238 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 239 240 /*Chip select 5 - PIB*/ 241 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 242 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 243 244 #define CONFIG_SYS_INIT_RAM_LOCK 1 245 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 246 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 247 248 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 249 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 250 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 251 252 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 253 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 254 255 /* Serial Port */ 256 #define CONFIG_CONS_INDEX 1 257 #undef CONFIG_SERIAL_SOFTWARE_FIFO 258 #define CONFIG_SYS_NS16550 259 #define CONFIG_SYS_NS16550_SERIAL 260 #define CONFIG_SYS_NS16550_REG_SIZE 1 261 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 262 263 #define CONFIG_SYS_BAUDRATE_TABLE \ 264 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 265 266 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 267 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 268 269 /* Use the HUSH parser*/ 270 #define CONFIG_SYS_HUSH_PARSER 271 #ifdef CONFIG_SYS_HUSH_PARSER 272 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 273 #endif 274 275 /* pass open firmware flat tree */ 276 #define CONFIG_OF_LIBFDT 1 277 #define CONFIG_OF_BOARD_SETUP 1 278 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 279 280 #define CONFIG_SYS_64BIT_VSPRINTF 1 281 #define CONFIG_SYS_64BIT_STRTOUL 1 282 283 /* 284 * I2C 285 */ 286 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 287 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 288 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 289 #define CONFIG_I2C_MULTI_BUS 290 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 291 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 292 #define CONFIG_SYS_I2C_SLAVE 0x7F 293 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 294 #define CONFIG_SYS_I2C_OFFSET 0x3000 295 #define CONFIG_SYS_I2C2_OFFSET 0x3100 296 297 /* 298 * General PCI 299 * Memory Addresses are mapped 1-1. I/O is mapped from 0 300 */ 301 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 302 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 303 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 304 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 305 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 306 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 307 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 308 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 309 310 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 311 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 312 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 313 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 314 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 315 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 316 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 317 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 318 319 #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 320 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 321 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 322 323 #ifdef CONFIG_QE 324 /* 325 * QE UEC ethernet configuration 326 */ 327 #define CONFIG_UEC_ETH 328 #ifndef CONFIG_TSEC_ENET 329 #define CONFIG_ETHPRIME "FSL UEC0" 330 #endif 331 #define CONFIG_PHY_MODE_NEED_CHANGE 332 #define CONFIG_eTSEC_MDIO_BUS 333 334 #ifdef CONFIG_eTSEC_MDIO_BUS 335 #define CONFIG_MIIM_ADDRESS 0xE0024520 336 #endif 337 338 #define CONFIG_UEC_ETH1 /* GETH1 */ 339 340 #ifdef CONFIG_UEC_ETH1 341 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 342 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 343 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 344 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 345 #define CONFIG_SYS_UEC1_PHY_ADDR 7 346 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID 347 #endif 348 349 #define CONFIG_UEC_ETH2 /* GETH2 */ 350 351 #ifdef CONFIG_UEC_ETH2 352 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 353 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 354 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 355 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 356 #define CONFIG_SYS_UEC2_PHY_ADDR 1 357 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID 358 #endif 359 #endif /* CONFIG_QE */ 360 361 #if defined(CONFIG_PCI) 362 363 #define CONFIG_NET_MULTI 364 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 365 366 #undef CONFIG_EEPRO100 367 #undef CONFIG_TULIP 368 369 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 370 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 371 372 #endif /* CONFIG_PCI */ 373 374 #ifndef CONFIG_NET_MULTI 375 #define CONFIG_NET_MULTI 1 376 #endif 377 378 #if defined(CONFIG_TSEC_ENET) 379 380 #define CONFIG_MII 1 /* MII PHY management */ 381 #define CONFIG_TSEC1 1 382 #define CONFIG_TSEC1_NAME "eTSEC0" 383 #define CONFIG_TSEC2 1 384 #define CONFIG_TSEC2_NAME "eTSEC1" 385 386 #define TSEC1_PHY_ADDR 2 387 #define TSEC2_PHY_ADDR 3 388 389 #define TSEC1_PHYIDX 0 390 #define TSEC2_PHYIDX 0 391 392 #define TSEC1_FLAGS TSEC_GIGABIT 393 #define TSEC2_FLAGS TSEC_GIGABIT 394 395 /* Options are: eTSEC[0-1] */ 396 #define CONFIG_ETHPRIME "eTSEC0" 397 398 #endif /* CONFIG_TSEC_ENET */ 399 400 /* 401 * Environment 402 */ 403 #define CONFIG_ENV_IS_IN_FLASH 1 404 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 405 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 406 #define CONFIG_ENV_SIZE 0x2000 407 408 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 409 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 410 411 412 /* 413 * BOOTP options 414 */ 415 #define CONFIG_BOOTP_BOOTFILESIZE 416 #define CONFIG_BOOTP_BOOTPATH 417 #define CONFIG_BOOTP_GATEWAY 418 #define CONFIG_BOOTP_HOSTNAME 419 420 421 /* 422 * Command line configuration. 423 */ 424 #include <config_cmd_default.h> 425 426 #define CONFIG_CMD_PING 427 #define CONFIG_CMD_I2C 428 #define CONFIG_CMD_MII 429 #define CONFIG_CMD_ELF 430 #define CONFIG_CMD_IRQ 431 #define CONFIG_CMD_SETEXPR 432 433 #if defined(CONFIG_PCI) 434 #define CONFIG_CMD_PCI 435 #endif 436 437 438 #undef CONFIG_WATCHDOG /* watchdog disabled */ 439 440 /* 441 * Miscellaneous configurable options 442 */ 443 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 444 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 445 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 446 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 447 #if defined(CONFIG_CMD_KGDB) 448 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 449 #else 450 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 451 #endif 452 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 453 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 454 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 455 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 456 457 /* 458 * For booting Linux, the board info and command line data 459 * have to be in the first 8 MB of memory, since this is 460 * the maximum mapped by the Linux kernel during initialization. 461 */ 462 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 463 464 /* 465 * Internal Definitions 466 * 467 * Boot Flags 468 */ 469 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 470 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 471 472 #if defined(CONFIG_CMD_KGDB) 473 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 474 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 475 #endif 476 477 /* 478 * Environment Configuration 479 */ 480 481 /* The mac addresses for all ethernet interface */ 482 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 483 #define CONFIG_HAS_ETH0 484 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 485 #define CONFIG_HAS_ETH1 486 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 487 #define CONFIG_HAS_ETH2 488 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 489 #define CONFIG_HAS_ETH3 490 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 491 #endif 492 493 #define CONFIG_IPADDR 192.168.1.253 494 495 #define CONFIG_HOSTNAME unknown 496 #define CONFIG_ROOTPATH /nfsroot 497 #define CONFIG_BOOTFILE your.uImage 498 499 #define CONFIG_SERVERIP 192.168.1.1 500 #define CONFIG_GATEWAYIP 192.168.1.1 501 #define CONFIG_NETMASK 255.255.255.0 502 503 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 504 505 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 506 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 507 508 #define CONFIG_BAUDRATE 115200 509 510 #define CONFIG_EXTRA_ENV_SETTINGS \ 511 "netdev=eth0\0" \ 512 "consoledev=ttyS0\0" \ 513 "ramdiskaddr=600000\0" \ 514 "ramdiskfile=your.ramdisk.u-boot\0" \ 515 "fdtaddr=400000\0" \ 516 "fdtfile=your.fdt.dtb\0" \ 517 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 518 "nfsroot=$serverip:$rootpath " \ 519 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 520 "console=$consoledev,$baudrate $othbootargs\0" \ 521 "ramargs=setenv bootargs root=/dev/ram rw " \ 522 "console=$consoledev,$baudrate $othbootargs\0" \ 523 524 525 #define CONFIG_NFSBOOTCOMMAND \ 526 "run nfsargs;" \ 527 "tftp $loadaddr $bootfile;" \ 528 "tftp $fdtaddr $fdtfile;" \ 529 "bootm $loadaddr - $fdtaddr" 530 531 532 #define CONFIG_RAMBOOTCOMMAND \ 533 "run ramargs;" \ 534 "tftp $ramdiskaddr $ramdiskfile;" \ 535 "tftp $loadaddr $bootfile;" \ 536 "bootm $loadaddr $ramdiskaddr" 537 538 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 539 540 #endif /* __CONFIG_H */ 541