1 /* 2 * Copyright 2004-2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8568mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8568 1 /* MPC8568 specific */ 34 #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 35 36 #define CONFIG_PCI 37 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 38 #define CONFIG_QE /* Enable QE */ 39 #define CONFIG_ENV_OVERWRITE 40 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 41 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 42 /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ 43 44 /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ 45 /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ 46 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 47 48 49 /* 50 * When initializing flash, if we cannot find the manufacturer ID, 51 * assume this is the AMD flash associated with the MDS board. 52 * This allows booting from a promjet. 53 */ 54 #define CONFIG_ASSUME_AMD_FLASH 55 56 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 57 58 #ifndef __ASSEMBLY__ 59 extern unsigned long get_clock_freq(void); 60 #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 61 #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 62 63 /* 64 * These can be toggled for performance analysis, otherwise use default. 65 */ 66 #define CONFIG_L2_CACHE /* toggle L2 cache */ 67 #define CONFIG_BTB /* toggle branch predition */ 68 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 69 70 /* 71 * Only possible on E500 Version 2 or newer cores. 72 */ 73 #define CONFIG_ENABLE_36BIT_PHYS 1 74 75 76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 77 78 #undef CFG_DRAM_TEST /* memory test, takes time */ 79 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 80 #define CFG_MEMTEST_END 0x00400000 81 82 /* 83 * Base addresses -- Note these are effective addresses where the 84 * actual resources get mapped (not physical addresses) 85 */ 86 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 87 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 88 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 89 90 /* 91 * DDR Setup 92 */ 93 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 94 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 95 96 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 97 98 /* 99 * Make sure required options are set 100 */ 101 #ifndef CONFIG_SPD_EEPROM 102 #error ("CONFIG_SPD_EEPROM is required") 103 #endif 104 105 #undef CONFIG_CLOCKS_IN_MHZ 106 107 108 /* 109 * Local Bus Definitions 110 */ 111 112 /* 113 * FLASH on the Local Bus 114 * Two banks, 8M each, using the CFI driver. 115 * Boot from BR0/OR0 bank at 0xff00_0000 116 * Alternate BR1/OR1 bank at 0xff80_0000 117 * 118 * BR0, BR1: 119 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 120 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 121 * Port Size = 16 bits = BRx[19:20] = 10 122 * Use GPCM = BRx[24:26] = 000 123 * Valid = BRx[31] = 1 124 * 125 * 0 4 8 12 16 20 24 28 126 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 127 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 128 * 129 * OR0, OR1: 130 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 131 * Reserved ORx[17:18] = 11, confusion here? 132 * CSNT = ORx[20] = 1 133 * ACS = half cycle delay = ORx[21:22] = 11 134 * SCY = 6 = ORx[24:27] = 0110 135 * TRLX = use relaxed timing = ORx[29] = 1 136 * EAD = use external address latch delay = OR[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 140 */ 141 #define CFG_BCSR_BASE 0xf8000000 142 143 #define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 144 145 /*Chip select 0 - Flash*/ 146 #define CFG_BR0_PRELIM 0xfe001001 147 #define CFG_OR0_PRELIM 0xfe006ff7 148 149 /*Chip slelect 1 - BCSR*/ 150 #define CFG_BR1_PRELIM 0xf8000801 151 #define CFG_OR1_PRELIM 0xffffe9f7 152 153 /*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */ 154 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 155 #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ 156 #undef CFG_FLASH_CHECKSUM 157 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 158 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 159 160 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 161 162 #define CFG_FLASH_CFI_DRIVER 163 #define CFG_FLASH_CFI 164 #define CFG_FLASH_EMPTY_INFO 165 166 167 /* 168 * SDRAM on the LocalBus 169 */ 170 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 171 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 172 173 174 /*Chip select 2 - SDRAM*/ 175 #define CFG_BR2_PRELIM 0xf0001861 176 #define CFG_OR2_PRELIM 0xfc006901 177 178 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 179 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 180 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 181 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 182 183 /* 184 * LSDMR masks 185 */ 186 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 187 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 188 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 189 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 190 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 191 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 192 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 193 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 194 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 195 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 196 197 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 198 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 199 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 200 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 201 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 202 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 203 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 204 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 205 206 /* 207 * Common settings for all Local Bus SDRAM commands. 208 * At run time, either BSMA1516 (for CPU 1.1) 209 * or BSMA1617 (for CPU 1.0) (old) 210 * is OR'ed in too. 211 */ 212 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 213 | CFG_LBC_LSDMR_PRETOACT7 \ 214 | CFG_LBC_LSDMR_ACTTORW7 \ 215 | CFG_LBC_LSDMR_BL8 \ 216 | CFG_LBC_LSDMR_WRC4 \ 217 | CFG_LBC_LSDMR_CL3 \ 218 | CFG_LBC_LSDMR_RFEN \ 219 ) 220 221 /* 222 * The bcsr registers are connected to CS3 on MDS. 223 * The new memory map places bcsr at 0xf8000000. 224 * 225 * For BR3, need: 226 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 227 * port-size = 8-bits = BR[19:20] = 01 228 * no parity checking = BR[21:22] = 00 229 * GPMC for MSEL = BR[24:26] = 000 230 * Valid = BR[31] = 1 231 * 232 * 0 4 8 12 16 20 24 28 233 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 234 * 235 * For OR3, need: 236 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 237 * disable buffer ctrl OR[19] = 0 238 * CSNT OR[20] = 1 239 * ACS OR[21:22] = 11 240 * XACS OR[23] = 1 241 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 242 * SETA OR[28] = 0 243 * TRLX OR[29] = 1 244 * EHTR OR[30] = 1 245 * EAD extra time OR[31] = 1 246 * 247 * 0 4 8 12 16 20 24 28 248 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 249 */ 250 #define CFG_BCSR (0xf8000000) 251 252 /*Chip slelect 4 - PIB*/ 253 #define CFG_BR4_PRELIM 0xf8008801 254 #define CFG_OR4_PRELIM 0xffffe9f7 255 256 /*Chip select 5 - PIB*/ 257 #define CFG_BR5_PRELIM 0xf8010801 258 #define CFG_OR5_PRELIM 0xffff69f7 259 260 #define CONFIG_L1_INIT_RAM 261 #define CFG_INIT_RAM_LOCK 1 262 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 263 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 264 265 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 266 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 267 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 268 269 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 270 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 271 272 /* Serial Port */ 273 #define CONFIG_CONS_INDEX 1 274 #undef CONFIG_SERIAL_SOFTWARE_FIFO 275 #define CFG_NS16550 276 #define CFG_NS16550_SERIAL 277 #define CFG_NS16550_REG_SIZE 1 278 #define CFG_NS16550_CLK get_bus_freq(0) 279 280 #define CFG_BAUDRATE_TABLE \ 281 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 282 283 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 284 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 285 286 /* Use the HUSH parser*/ 287 #define CFG_HUSH_PARSER 288 #ifdef CFG_HUSH_PARSER 289 #define CFG_PROMPT_HUSH_PS2 "> " 290 #endif 291 292 /* pass open firmware flat tree */ 293 #define CONFIG_OF_FLAT_TREE 1 294 #define CONFIG_OF_BOARD_SETUP 1 295 296 #define OF_CPU "PowerPC,8568@0" 297 #define OF_SOC "soc8568@e0000000" 298 #define OF_QE "qe@e0080000" 299 #define OF_TBCLK (bd->bi_busfreq / 8) 300 #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" 301 302 /* 303 * I2C 304 */ 305 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 306 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 307 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 308 #define CONFIG_I2C_MULTI_BUS 309 #define CONFIG_I2C_CMD_TREE 310 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 311 #define CFG_I2C_EEPROM_ADDR 0x52 312 #define CFG_I2C_SLAVE 0x7F 313 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 314 #define CFG_I2C_OFFSET 0x3000 315 #define CFG_I2C2_OFFSET 0x3100 316 317 /* 318 * General PCI 319 * Memory Addresses are mapped 1-1. I/O is mapped from 0 320 */ 321 #define CFG_PCI1_MEM_BASE 0x80000000 322 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 323 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 324 #define CFG_PCI1_IO_BASE 0x00000000 325 #define CFG_PCI1_IO_PHYS 0xe2000000 326 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ 327 328 #define CFG_PEX_MEM_BASE 0xa0000000 329 #define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE 330 #define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */ 331 #define CFG_PEX_IO_BASE 0x00000000 332 #define CFG_PEX_IO_PHYS 0xe2800000 333 #define CFG_PEX_IO_SIZE 0x00800000 /* 8M */ 334 335 #define CFG_SRIO_MEM_BASE 0xc0000000 336 337 #if defined(CONFIG_PCI) 338 339 #define CONFIG_NET_MULTI 340 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 341 342 #ifdef CONFIG_QE 343 /* 344 * QE UEC ethernet configuration 345 */ 346 #define CONFIG_UEC_ETH 347 #ifndef CONFIG_TSEC_ENET 348 #define CONFIG_ETHPRIME "FSL UEC0" 349 #endif 350 #define CONFIG_PHY_MODE_NEED_CHANGE 351 #define CONFIG_eTSEC_MDIO_BUS 352 353 #ifdef CONFIG_eTSEC_MDIO_BUS 354 #define CONFIG_MIIM_ADDRESS 0xE0024520 355 #endif 356 357 #define CONFIG_UEC_ETH1 /* GETH1 */ 358 359 #ifdef CONFIG_UEC_ETH1 360 #define CFG_UEC1_UCC_NUM 0 /* UCC1 */ 361 #define CFG_UEC1_RX_CLK QE_CLK_NONE 362 #define CFG_UEC1_TX_CLK QE_CLK16 363 #define CFG_UEC1_ETH_TYPE GIGA_ETH 364 #define CFG_UEC1_PHY_ADDR 7 365 #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII 366 #endif 367 368 #define CONFIG_UEC_ETH2 /* GETH2 */ 369 370 #ifdef CONFIG_UEC_ETH2 371 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ 372 #define CFG_UEC2_RX_CLK QE_CLK_NONE 373 #define CFG_UEC2_TX_CLK QE_CLK16 374 #define CFG_UEC2_ETH_TYPE GIGA_ETH 375 #define CFG_UEC2_PHY_ADDR 1 376 #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII 377 #endif 378 #endif /* CONFIG_QE */ 379 380 #undef CONFIG_EEPRO100 381 #undef CONFIG_TULIP 382 383 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 384 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 385 386 #endif /* CONFIG_PCI */ 387 388 #ifndef CONFIG_NET_MULTI 389 #define CONFIG_NET_MULTI 1 390 #endif 391 392 #if defined(CONFIG_TSEC_ENET) 393 394 #define CONFIG_MII 1 /* MII PHY management */ 395 #define CONFIG_TSEC1 1 396 #define CONFIG_TSEC1_NAME "eTSEC0" 397 #define CONFIG_TSEC2 1 398 #define CONFIG_TSEC2_NAME "eTSEC1" 399 400 #define TSEC1_PHY_ADDR 2 401 #define TSEC2_PHY_ADDR 3 402 403 #define TSEC1_PHYIDX 0 404 #define TSEC2_PHYIDX 0 405 406 #define TSEC1_FLAGS TSEC_GIGABIT 407 #define TSEC2_FLAGS TSEC_GIGABIT 408 409 /* Options are: eTSEC[0-1] */ 410 #define CONFIG_ETHPRIME "eTSEC0" 411 412 #endif /* CONFIG_TSEC_ENET */ 413 414 /* 415 * Environment 416 */ 417 #define CFG_ENV_IS_IN_FLASH 1 418 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 419 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 420 #define CFG_ENV_SIZE 0x2000 421 422 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 423 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 424 425 426 /* 427 * BOOTP options 428 */ 429 #define CONFIG_BOOTP_BOOTFILESIZE 430 #define CONFIG_BOOTP_BOOTPATH 431 #define CONFIG_BOOTP_GATEWAY 432 #define CONFIG_BOOTP_HOSTNAME 433 434 435 /* 436 * Command line configuration. 437 */ 438 #include <config_cmd_default.h> 439 440 #define CONFIG_CMD_PING 441 #define CONFIG_CMD_I2C 442 #define CONFIG_CMD_MII 443 444 #if defined(CONFIG_PCI) 445 #define CONFIG_CMD_PCI 446 #endif 447 448 449 #undef CONFIG_WATCHDOG /* watchdog disabled */ 450 451 /* 452 * Miscellaneous configurable options 453 */ 454 #define CFG_LONGHELP /* undef to save memory */ 455 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 456 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 457 #if defined(CONFIG_CMD_KGDB) 458 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 459 #else 460 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 461 #endif 462 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 463 #define CFG_MAXARGS 16 /* max number of command args */ 464 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 465 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 466 467 /* 468 * For booting Linux, the board info and command line data 469 * have to be in the first 8 MB of memory, since this is 470 * the maximum mapped by the Linux kernel during initialization. 471 */ 472 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 473 474 /* Cache Configuration */ 475 #define CFG_DCACHE_SIZE 32768 476 #define CFG_CACHELINE_SIZE 32 477 #if defined(CONFIG_CMD_KGDB) 478 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 479 #endif 480 481 /* 482 * Internal Definitions 483 * 484 * Boot Flags 485 */ 486 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 487 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 488 489 #if defined(CONFIG_CMD_KGDB) 490 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 491 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 492 #endif 493 494 /* 495 * Environment Configuration 496 */ 497 498 /* The mac addresses for all ethernet interface */ 499 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 500 #define CONFIG_HAS_ETH0 501 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 502 #define CONFIG_HAS_ETH1 503 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 504 #define CONFIG_HAS_ETH2 505 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 506 #define CONFIG_HAS_ETH3 507 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 508 #endif 509 510 #define CONFIG_IPADDR 192.168.1.253 511 512 #define CONFIG_HOSTNAME unknown 513 #define CONFIG_ROOTPATH /nfsroot 514 #define CONFIG_BOOTFILE your.uImage 515 516 #define CONFIG_SERVERIP 192.168.1.1 517 #define CONFIG_GATEWAYIP 192.168.1.1 518 #define CONFIG_NETMASK 255.255.255.0 519 520 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 521 522 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 523 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 524 525 #define CONFIG_BAUDRATE 115200 526 527 #define CONFIG_EXTRA_ENV_SETTINGS \ 528 "netdev=eth0\0" \ 529 "consoledev=ttyS0\0" \ 530 "ramdiskaddr=600000\0" \ 531 "ramdiskfile=your.ramdisk.u-boot\0" \ 532 "fdtaddr=400000\0" \ 533 "fdtfile=your.fdt.dtb\0" \ 534 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 535 "nfsroot=$serverip:$rootpath " \ 536 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 537 "console=$consoledev,$baudrate $othbootargs\0" \ 538 "ramargs=setenv bootargs root=/dev/ram rw " \ 539 "console=$consoledev,$baudrate $othbootargs\0" \ 540 541 542 #define CONFIG_NFSBOOTCOMMAND \ 543 "run nfsargs;" \ 544 "tftp $loadaddr $bootfile;" \ 545 "tftp $fdtaddr $fdtfile;" \ 546 "bootm $loadaddr - $fdtaddr" 547 548 549 #define CONFIG_RAMBOOTCOMMAND \ 550 "run ramargs;" \ 551 "tftp $ramdiskaddr $ramdiskfile;" \ 552 "tftp $loadaddr $bootfile;" \ 553 "bootm $loadaddr $ramdiskaddr" 554 555 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 556 557 #endif /* __CONFIG_H */ 558