1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 #define CONFIG_SYS_GENERIC_BOARD 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 /* High Level Configuration Options */ 25 #define CONFIG_BOOKE 1 /* BOOKE */ 26 #define CONFIG_E500 1 /* BOOKE e500 family */ 27 #define CONFIG_CPM2 1 /* has CPM2 */ 28 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 29 #define CONFIG_MPC8560 1 30 31 /* 32 * default CCARBAR is at 0xff700000 33 * assume U-Boot is less than 0.5MB 34 */ 35 #define CONFIG_SYS_TEXT_BASE 0xfff80000 36 37 #define CONFIG_PCI 38 #define CONFIG_PCI_INDIRECT_BRIDGE 39 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 44 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 45 46 /* 47 * sysclk for MPC85xx 48 * 49 * Two valid values are: 50 * 33000000 51 * 66000000 52 * 53 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 54 * is likely the desired value here, so that is now the default. 55 * The board, however, can run at 66MHz. In any event, this value 56 * must match the settings of some switches. Details can be found 57 * in the README.mpc85xxads. 58 */ 59 60 #ifndef CONFIG_SYS_CLK_FREQ 61 #define CONFIG_SYS_CLK_FREQ 33000000 62 #endif 63 64 65 /* 66 * These can be toggled for performance analysis, otherwise use default. 67 */ 68 #define CONFIG_L2_CACHE /* toggle L2 cache */ 69 #define CONFIG_BTB /* toggle branch predition */ 70 71 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 72 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 74 #define CONFIG_SYS_MEMTEST_END 0x00400000 75 76 #define CONFIG_SYS_CCSRBAR 0xe0000000 77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 78 79 /* DDR Setup */ 80 #define CONFIG_SYS_FSL_DDR1 81 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 82 #define CONFIG_DDR_SPD 83 #undef CONFIG_FSL_DDR_INTERACTIVE 84 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 89 90 #define CONFIG_NUM_DDR_CONTROLLERS 1 91 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 92 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 93 94 /* I2C addresses of SPD EEPROMs */ 95 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 96 97 /* These are used when DDR doesn't use SPD. */ 98 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 99 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 100 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 101 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 102 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 103 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 104 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 105 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 106 107 /* 108 * SDRAM on the Local Bus 109 */ 110 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 111 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 112 113 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 114 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 115 116 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 119 #undef CONFIG_SYS_FLASH_CHECKSUM 120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 124 125 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 126 #define CONFIG_SYS_RAMBOOT 127 #else 128 #undef CONFIG_SYS_RAMBOOT 129 #endif 130 131 #define CONFIG_FLASH_CFI_DRIVER 132 #define CONFIG_SYS_FLASH_CFI 133 #define CONFIG_SYS_FLASH_EMPTY_INFO 134 135 #undef CONFIG_CLOCKS_IN_MHZ 136 137 138 /* 139 * Local Bus Definitions 140 */ 141 142 /* 143 * Base Register 2 and Option Register 2 configure SDRAM. 144 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 145 * 146 * For BR2, need: 147 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 148 * port-size = 32-bits = BR2[19:20] = 11 149 * no parity checking = BR2[21:22] = 00 150 * SDRAM for MSEL = BR2[24:26] = 011 151 * Valid = BR[31] = 1 152 * 153 * 0 4 8 12 16 20 24 28 154 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 155 * 156 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 157 * FIXME: the top 17 bits of BR2. 158 */ 159 160 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 161 162 /* 163 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 164 * 165 * For OR2, need: 166 * 64MB mask for AM, OR2[0:7] = 1111 1100 167 * XAM, OR2[17:18] = 11 168 * 9 columns OR2[19-21] = 010 169 * 13 rows OR2[23-25] = 100 170 * EAD set for extra time OR[31] = 1 171 * 172 * 0 4 8 12 16 20 24 28 173 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 174 */ 175 176 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 177 178 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 179 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 180 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 181 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 182 183 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 184 | LSDMR_RFCR5 \ 185 | LSDMR_PRETOACT3 \ 186 | LSDMR_ACTTORW3 \ 187 | LSDMR_BL8 \ 188 | LSDMR_WRC2 \ 189 | LSDMR_CL3 \ 190 | LSDMR_RFEN \ 191 ) 192 193 /* 194 * SDRAM Controller configuration sequence. 195 */ 196 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 197 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 198 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 199 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 200 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 201 202 203 /* 204 * 32KB, 8-bit wide for ADS config reg 205 */ 206 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 207 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 208 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 213 214 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 216 217 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 218 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 219 220 /* Serial Port */ 221 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 222 #undef CONFIG_CONS_NONE /* define if console on something else */ 223 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 224 225 #define CONFIG_BAUDRATE 115200 226 227 #define CONFIG_SYS_BAUDRATE_TABLE \ 228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 229 230 /* Use the HUSH parser */ 231 #define CONFIG_SYS_HUSH_PARSER 232 #ifdef CONFIG_SYS_HUSH_PARSER 233 #endif 234 235 /* pass open firmware flat tree */ 236 #define CONFIG_OF_LIBFDT 1 237 #define CONFIG_OF_BOARD_SETUP 1 238 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 239 240 /* 241 * I2C 242 */ 243 #define CONFIG_SYS_I2C 244 #define CONFIG_SYS_I2C_FSL 245 #define CONFIG_SYS_FSL_I2C_SPEED 400000 246 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 247 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 248 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 249 250 /* RapidIO MMU */ 251 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 252 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 253 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 254 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 255 256 /* 257 * General PCI 258 * Memory space is mapped 1-1, but I/O space must start from 0. 259 */ 260 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 261 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 262 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 263 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 264 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 265 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 266 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 267 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 268 269 #if defined(CONFIG_PCI) 270 271 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 272 273 #undef CONFIG_EEPRO100 274 #undef CONFIG_TULIP 275 276 #if !defined(CONFIG_PCI_PNP) 277 #define PCI_ENET0_IOADDR 0xe0000000 278 #define PCI_ENET0_MEMADDR 0xe0000000 279 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 280 #endif 281 282 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 283 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 284 285 #endif /* CONFIG_PCI */ 286 287 288 #ifdef CONFIG_TSEC_ENET 289 290 #ifndef CONFIG_MII 291 #define CONFIG_MII 1 /* MII PHY management */ 292 #endif 293 #define CONFIG_TSEC1 1 294 #define CONFIG_TSEC1_NAME "TSEC0" 295 #define CONFIG_TSEC2 1 296 #define CONFIG_TSEC2_NAME "TSEC1" 297 #define TSEC1_PHY_ADDR 0 298 #define TSEC2_PHY_ADDR 1 299 #define TSEC1_PHYIDX 0 300 #define TSEC2_PHYIDX 0 301 #define TSEC1_FLAGS TSEC_GIGABIT 302 #define TSEC2_FLAGS TSEC_GIGABIT 303 304 /* Options are: TSEC[0-1] */ 305 #define CONFIG_ETHPRIME "TSEC0" 306 307 #endif /* CONFIG_TSEC_ENET */ 308 309 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 310 311 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 312 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 313 314 #if (CONFIG_ETHER_INDEX == 2) 315 /* 316 * - Rx-CLK is CLK13 317 * - Tx-CLK is CLK14 318 * - Select bus for bd/buffers 319 * - Full duplex 320 */ 321 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 322 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 323 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 324 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 325 #define FETH2_RST 0x01 326 #elif (CONFIG_ETHER_INDEX == 3) 327 /* need more definitions here for FE3 */ 328 #define FETH3_RST 0x80 329 #endif /* CONFIG_ETHER_INDEX */ 330 331 #ifndef CONFIG_MII 332 #define CONFIG_MII 1 /* MII PHY management */ 333 #endif 334 335 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 336 337 /* 338 * GPIO pins used for bit-banged MII communications 339 */ 340 #define MDIO_PORT 2 /* Port C */ 341 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 342 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 343 #define MDC_DECLARE MDIO_DECLARE 344 345 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 346 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 347 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 348 349 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 350 else iop->pdat &= ~0x00400000 351 352 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 353 else iop->pdat &= ~0x00200000 354 355 #define MIIDELAY udelay(1) 356 357 #endif 358 359 360 /* 361 * Environment 362 */ 363 #ifndef CONFIG_SYS_RAMBOOT 364 #define CONFIG_ENV_IS_IN_FLASH 1 365 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 366 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 367 #define CONFIG_ENV_SIZE 0x2000 368 #else 369 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 370 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 371 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 372 #define CONFIG_ENV_SIZE 0x2000 373 #endif 374 375 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 376 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 377 378 /* 379 * BOOTP options 380 */ 381 #define CONFIG_BOOTP_BOOTFILESIZE 382 #define CONFIG_BOOTP_BOOTPATH 383 #define CONFIG_BOOTP_GATEWAY 384 #define CONFIG_BOOTP_HOSTNAME 385 386 387 /* 388 * Command line configuration. 389 */ 390 #define CONFIG_CMD_PING 391 #define CONFIG_CMD_I2C 392 #define CONFIG_CMD_ELF 393 #define CONFIG_CMD_IRQ 394 #define CONFIG_CMD_REGINFO 395 396 #if defined(CONFIG_PCI) 397 #define CONFIG_CMD_PCI 398 #endif 399 400 #if defined(CONFIG_ETHER_ON_FCC) 401 #define CONFIG_CMD_MII 402 #endif 403 404 #undef CONFIG_WATCHDOG /* watchdog disabled */ 405 406 /* 407 * Miscellaneous configurable options 408 */ 409 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 410 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 411 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 412 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 413 414 #if defined(CONFIG_CMD_KGDB) 415 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 416 #else 417 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 418 #endif 419 420 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 421 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 422 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 423 424 /* 425 * For booting Linux, the board info and command line data 426 * have to be in the first 64 MB of memory, since this is 427 * the maximum mapped by the Linux kernel during initialization. 428 */ 429 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 430 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 431 432 #if defined(CONFIG_CMD_KGDB) 433 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 434 #endif 435 436 437 /* 438 * Environment Configuration 439 */ 440 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 441 #define CONFIG_HAS_ETH0 442 #define CONFIG_HAS_ETH1 443 #define CONFIG_HAS_ETH2 444 #define CONFIG_HAS_ETH3 445 #endif 446 447 #define CONFIG_IPADDR 192.168.1.253 448 449 #define CONFIG_HOSTNAME unknown 450 #define CONFIG_ROOTPATH "/nfsroot" 451 #define CONFIG_BOOTFILE "your.uImage" 452 453 #define CONFIG_SERVERIP 192.168.1.1 454 #define CONFIG_GATEWAYIP 192.168.1.1 455 #define CONFIG_NETMASK 255.255.255.0 456 457 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 458 459 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 460 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 461 462 #define CONFIG_BAUDRATE 115200 463 464 #define CONFIG_EXTRA_ENV_SETTINGS \ 465 "netdev=eth0\0" \ 466 "consoledev=ttyCPM\0" \ 467 "ramdiskaddr=1000000\0" \ 468 "ramdiskfile=your.ramdisk.u-boot\0" \ 469 "fdtaddr=400000\0" \ 470 "fdtfile=mpc8560ads.dtb\0" 471 472 #define CONFIG_NFSBOOTCOMMAND \ 473 "setenv bootargs root=/dev/nfs rw " \ 474 "nfsroot=$serverip:$rootpath " \ 475 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 476 "console=$consoledev,$baudrate $othbootargs;" \ 477 "tftp $loadaddr $bootfile;" \ 478 "tftp $fdtaddr $fdtfile;" \ 479 "bootm $loadaddr - $fdtaddr" 480 481 #define CONFIG_RAMBOOTCOMMAND \ 482 "setenv bootargs root=/dev/ram rw " \ 483 "console=$consoledev,$baudrate $othbootargs;" \ 484 "tftp $ramdiskaddr $ramdiskfile;" \ 485 "tftp $loadaddr $bootfile;" \ 486 "tftp $fdtaddr $fdtfile;" \ 487 "bootm $loadaddr $ramdiskaddr $fdtaddr" 488 489 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 490 491 #endif /* __CONFIG_H */ 492