1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_CPM2 1 /* has CPM2 */ 25 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 26 #define CONFIG_MPC8560 1 27 28 /* 29 * default CCARBAR is at 0xff700000 30 * assume U-Boot is less than 0.5MB 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0xfff80000 33 34 #define CONFIG_PCI 35 #define CONFIG_PCI_INDIRECT_BRIDGE 36 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 37 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 38 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 39 #define CONFIG_ENV_OVERWRITE 40 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 41 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 42 43 /* 44 * sysclk for MPC85xx 45 * 46 * Two valid values are: 47 * 33000000 48 * 66000000 49 * 50 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 51 * is likely the desired value here, so that is now the default. 52 * The board, however, can run at 66MHz. In any event, this value 53 * must match the settings of some switches. Details can be found 54 * in the README.mpc85xxads. 55 */ 56 57 #ifndef CONFIG_SYS_CLK_FREQ 58 #define CONFIG_SYS_CLK_FREQ 33000000 59 #endif 60 61 62 /* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65 #define CONFIG_L2_CACHE /* toggle L2 cache */ 66 #define CONFIG_BTB /* toggle branch predition */ 67 68 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 69 70 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 71 #define CONFIG_SYS_MEMTEST_END 0x00400000 72 73 #define CONFIG_SYS_CCSRBAR 0xe0000000 74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 75 76 /* DDR Setup */ 77 #define CONFIG_SYS_FSL_DDR1 78 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 79 #define CONFIG_DDR_SPD 80 #undef CONFIG_FSL_DDR_INTERACTIVE 81 82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 83 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 87 #define CONFIG_NUM_DDR_CONTROLLERS 1 88 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 89 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 90 91 /* I2C addresses of SPD EEPROMs */ 92 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 93 94 /* These are used when DDR doesn't use SPD. */ 95 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 96 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 98 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 99 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 100 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 101 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 102 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 103 104 /* 105 * SDRAM on the Local Bus 106 */ 107 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 108 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 109 110 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 111 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 112 113 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 114 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 116 #undef CONFIG_SYS_FLASH_CHECKSUM 117 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 118 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 119 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 121 122 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 123 #define CONFIG_SYS_RAMBOOT 124 #else 125 #undef CONFIG_SYS_RAMBOOT 126 #endif 127 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_EMPTY_INFO 131 132 #undef CONFIG_CLOCKS_IN_MHZ 133 134 135 /* 136 * Local Bus Definitions 137 */ 138 139 /* 140 * Base Register 2 and Option Register 2 configure SDRAM. 141 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 142 * 143 * For BR2, need: 144 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 145 * port-size = 32-bits = BR2[19:20] = 11 146 * no parity checking = BR2[21:22] = 00 147 * SDRAM for MSEL = BR2[24:26] = 011 148 * Valid = BR[31] = 1 149 * 150 * 0 4 8 12 16 20 24 28 151 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 152 * 153 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 154 * FIXME: the top 17 bits of BR2. 155 */ 156 157 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 158 159 /* 160 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 161 * 162 * For OR2, need: 163 * 64MB mask for AM, OR2[0:7] = 1111 1100 164 * XAM, OR2[17:18] = 11 165 * 9 columns OR2[19-21] = 010 166 * 13 rows OR2[23-25] = 100 167 * EAD set for extra time OR[31] = 1 168 * 169 * 0 4 8 12 16 20 24 28 170 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 171 */ 172 173 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 174 175 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 176 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 177 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 178 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 179 180 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 181 | LSDMR_RFCR5 \ 182 | LSDMR_PRETOACT3 \ 183 | LSDMR_ACTTORW3 \ 184 | LSDMR_BL8 \ 185 | LSDMR_WRC2 \ 186 | LSDMR_CL3 \ 187 | LSDMR_RFEN \ 188 ) 189 190 /* 191 * SDRAM Controller configuration sequence. 192 */ 193 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 194 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 195 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 196 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 197 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 198 199 200 /* 201 * 32KB, 8-bit wide for ADS config reg 202 */ 203 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 204 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 205 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 206 207 #define CONFIG_SYS_INIT_RAM_LOCK 1 208 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 209 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 210 211 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 213 214 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 215 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 216 217 /* Serial Port */ 218 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 219 #undef CONFIG_CONS_NONE /* define if console on something else */ 220 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 221 222 #define CONFIG_BAUDRATE 115200 223 224 #define CONFIG_SYS_BAUDRATE_TABLE \ 225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 226 227 /* Use the HUSH parser */ 228 #define CONFIG_SYS_HUSH_PARSER 229 #ifdef CONFIG_SYS_HUSH_PARSER 230 #endif 231 232 /* pass open firmware flat tree */ 233 #define CONFIG_OF_LIBFDT 1 234 #define CONFIG_OF_BOARD_SETUP 1 235 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 236 237 /* 238 * I2C 239 */ 240 #define CONFIG_SYS_I2C 241 #define CONFIG_SYS_I2C_FSL 242 #define CONFIG_SYS_FSL_I2C_SPEED 400000 243 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 244 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 245 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 246 247 /* RapidIO MMU */ 248 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 249 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 250 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 251 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 252 253 /* 254 * General PCI 255 * Memory space is mapped 1-1, but I/O space must start from 0. 256 */ 257 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 258 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 259 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 261 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 262 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 263 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 264 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 265 266 #if defined(CONFIG_PCI) 267 268 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 269 270 #undef CONFIG_EEPRO100 271 #undef CONFIG_TULIP 272 273 #if !defined(CONFIG_PCI_PNP) 274 #define PCI_ENET0_IOADDR 0xe0000000 275 #define PCI_ENET0_MEMADDR 0xe0000000 276 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 277 #endif 278 279 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 280 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 281 282 #endif /* CONFIG_PCI */ 283 284 285 #ifdef CONFIG_TSEC_ENET 286 287 #ifndef CONFIG_MII 288 #define CONFIG_MII 1 /* MII PHY management */ 289 #endif 290 #define CONFIG_TSEC1 1 291 #define CONFIG_TSEC1_NAME "TSEC0" 292 #define CONFIG_TSEC2 1 293 #define CONFIG_TSEC2_NAME "TSEC1" 294 #define TSEC1_PHY_ADDR 0 295 #define TSEC2_PHY_ADDR 1 296 #define TSEC1_PHYIDX 0 297 #define TSEC2_PHYIDX 0 298 #define TSEC1_FLAGS TSEC_GIGABIT 299 #define TSEC2_FLAGS TSEC_GIGABIT 300 301 /* Options are: TSEC[0-1] */ 302 #define CONFIG_ETHPRIME "TSEC0" 303 304 #endif /* CONFIG_TSEC_ENET */ 305 306 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 307 308 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 309 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 310 311 #if (CONFIG_ETHER_INDEX == 2) 312 /* 313 * - Rx-CLK is CLK13 314 * - Tx-CLK is CLK14 315 * - Select bus for bd/buffers 316 * - Full duplex 317 */ 318 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 319 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 320 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 321 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 322 #define FETH2_RST 0x01 323 #elif (CONFIG_ETHER_INDEX == 3) 324 /* need more definitions here for FE3 */ 325 #define FETH3_RST 0x80 326 #endif /* CONFIG_ETHER_INDEX */ 327 328 #ifndef CONFIG_MII 329 #define CONFIG_MII 1 /* MII PHY management */ 330 #endif 331 332 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 333 334 /* 335 * GPIO pins used for bit-banged MII communications 336 */ 337 #define MDIO_PORT 2 /* Port C */ 338 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 339 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 340 #define MDC_DECLARE MDIO_DECLARE 341 342 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 343 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 344 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 345 346 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 347 else iop->pdat &= ~0x00400000 348 349 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 350 else iop->pdat &= ~0x00200000 351 352 #define MIIDELAY udelay(1) 353 354 #endif 355 356 357 /* 358 * Environment 359 */ 360 #ifndef CONFIG_SYS_RAMBOOT 361 #define CONFIG_ENV_IS_IN_FLASH 1 362 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 363 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 364 #define CONFIG_ENV_SIZE 0x2000 365 #else 366 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 367 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 369 #define CONFIG_ENV_SIZE 0x2000 370 #endif 371 372 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 373 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 374 375 /* 376 * BOOTP options 377 */ 378 #define CONFIG_BOOTP_BOOTFILESIZE 379 #define CONFIG_BOOTP_BOOTPATH 380 #define CONFIG_BOOTP_GATEWAY 381 #define CONFIG_BOOTP_HOSTNAME 382 383 384 /* 385 * Command line configuration. 386 */ 387 #include <config_cmd_default.h> 388 389 #define CONFIG_CMD_PING 390 #define CONFIG_CMD_I2C 391 #define CONFIG_CMD_ELF 392 #define CONFIG_CMD_IRQ 393 #define CONFIG_CMD_SETEXPR 394 #define CONFIG_CMD_REGINFO 395 396 #if defined(CONFIG_PCI) 397 #define CONFIG_CMD_PCI 398 #endif 399 400 #if defined(CONFIG_ETHER_ON_FCC) 401 #define CONFIG_CMD_MII 402 #endif 403 404 #if defined(CONFIG_SYS_RAMBOOT) 405 #undef CONFIG_CMD_SAVEENV 406 #undef CONFIG_CMD_LOADS 407 #endif 408 409 410 #undef CONFIG_WATCHDOG /* watchdog disabled */ 411 412 /* 413 * Miscellaneous configurable options 414 */ 415 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 416 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 417 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 418 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 419 420 #if defined(CONFIG_CMD_KGDB) 421 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 422 #else 423 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 424 #endif 425 426 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 427 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 428 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 429 430 /* 431 * For booting Linux, the board info and command line data 432 * have to be in the first 64 MB of memory, since this is 433 * the maximum mapped by the Linux kernel during initialization. 434 */ 435 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 436 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 437 438 #if defined(CONFIG_CMD_KGDB) 439 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 440 #endif 441 442 443 /* 444 * Environment Configuration 445 */ 446 447 /* The mac addresses for all ethernet interface */ 448 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 449 #define CONFIG_HAS_ETH0 450 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 451 #define CONFIG_HAS_ETH1 452 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 453 #define CONFIG_HAS_ETH2 454 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 455 #define CONFIG_HAS_ETH3 456 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 457 #endif 458 459 #define CONFIG_IPADDR 192.168.1.253 460 461 #define CONFIG_HOSTNAME unknown 462 #define CONFIG_ROOTPATH "/nfsroot" 463 #define CONFIG_BOOTFILE "your.uImage" 464 465 #define CONFIG_SERVERIP 192.168.1.1 466 #define CONFIG_GATEWAYIP 192.168.1.1 467 #define CONFIG_NETMASK 255.255.255.0 468 469 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 470 471 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 472 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 473 474 #define CONFIG_BAUDRATE 115200 475 476 #define CONFIG_EXTRA_ENV_SETTINGS \ 477 "netdev=eth0\0" \ 478 "consoledev=ttyCPM\0" \ 479 "ramdiskaddr=1000000\0" \ 480 "ramdiskfile=your.ramdisk.u-boot\0" \ 481 "fdtaddr=400000\0" \ 482 "fdtfile=mpc8560ads.dtb\0" 483 484 #define CONFIG_NFSBOOTCOMMAND \ 485 "setenv bootargs root=/dev/nfs rw " \ 486 "nfsroot=$serverip:$rootpath " \ 487 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 488 "console=$consoledev,$baudrate $othbootargs;" \ 489 "tftp $loadaddr $bootfile;" \ 490 "tftp $fdtaddr $fdtfile;" \ 491 "bootm $loadaddr - $fdtaddr" 492 493 #define CONFIG_RAMBOOTCOMMAND \ 494 "setenv bootargs root=/dev/ram rw " \ 495 "console=$consoledev,$baudrate $othbootargs;" \ 496 "tftp $ramdiskaddr $ramdiskfile;" \ 497 "tftp $loadaddr $bootfile;" \ 498 "tftp $fdtaddr $fdtfile;" \ 499 "bootm $loadaddr $ramdiskaddr $fdtaddr" 500 501 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 502 503 #endif /* __CONFIG_H */ 504