1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_CPM2 1 /* has CPM2 */ 25 26 /* 27 * default CCARBAR is at 0xff700000 28 * assume U-Boot is less than 0.5MB 29 */ 30 #define CONFIG_SYS_TEXT_BASE 0xfff80000 31 32 #define CONFIG_PCI_INDIRECT_BRIDGE 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 35 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 36 #define CONFIG_ENV_OVERWRITE 37 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 38 39 /* 40 * sysclk for MPC85xx 41 * 42 * Two valid values are: 43 * 33000000 44 * 66000000 45 * 46 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 47 * is likely the desired value here, so that is now the default. 48 * The board, however, can run at 66MHz. In any event, this value 49 * must match the settings of some switches. Details can be found 50 * in the README.mpc85xxads. 51 */ 52 53 #ifndef CONFIG_SYS_CLK_FREQ 54 #define CONFIG_SYS_CLK_FREQ 33000000 55 #endif 56 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CONFIG_L2_CACHE /* toggle L2 cache */ 61 #define CONFIG_BTB /* toggle branch predition */ 62 63 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 64 65 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 66 #define CONFIG_SYS_MEMTEST_END 0x00400000 67 68 #define CONFIG_SYS_CCSRBAR 0xe0000000 69 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 70 71 /* DDR Setup */ 72 #define CONFIG_SYS_FSL_DDR1 73 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 74 #define CONFIG_DDR_SPD 75 #undef CONFIG_FSL_DDR_INTERACTIVE 76 77 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 78 79 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 81 82 #define CONFIG_NUM_DDR_CONTROLLERS 1 83 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 84 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 85 86 /* I2C addresses of SPD EEPROMs */ 87 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 88 89 /* These are used when DDR doesn't use SPD. */ 90 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 91 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 92 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 93 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 94 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 95 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 96 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 97 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 98 99 /* 100 * SDRAM on the Local Bus 101 */ 102 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 103 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 104 105 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 106 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 107 108 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 109 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 110 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 111 #undef CONFIG_SYS_FLASH_CHECKSUM 112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 114 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 116 117 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 118 #define CONFIG_SYS_RAMBOOT 119 #else 120 #undef CONFIG_SYS_RAMBOOT 121 #endif 122 123 #define CONFIG_FLASH_CFI_DRIVER 124 #define CONFIG_SYS_FLASH_CFI 125 #define CONFIG_SYS_FLASH_EMPTY_INFO 126 127 #undef CONFIG_CLOCKS_IN_MHZ 128 129 /* 130 * Local Bus Definitions 131 */ 132 133 /* 134 * Base Register 2 and Option Register 2 configure SDRAM. 135 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 136 * 137 * For BR2, need: 138 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 139 * port-size = 32-bits = BR2[19:20] = 11 140 * no parity checking = BR2[21:22] = 00 141 * SDRAM for MSEL = BR2[24:26] = 011 142 * Valid = BR[31] = 1 143 * 144 * 0 4 8 12 16 20 24 28 145 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 146 * 147 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 148 * FIXME: the top 17 bits of BR2. 149 */ 150 151 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 152 153 /* 154 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 155 * 156 * For OR2, need: 157 * 64MB mask for AM, OR2[0:7] = 1111 1100 158 * XAM, OR2[17:18] = 11 159 * 9 columns OR2[19-21] = 010 160 * 13 rows OR2[23-25] = 100 161 * EAD set for extra time OR[31] = 1 162 * 163 * 0 4 8 12 16 20 24 28 164 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 165 */ 166 167 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 168 169 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 170 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 171 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 172 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 173 174 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 175 | LSDMR_RFCR5 \ 176 | LSDMR_PRETOACT3 \ 177 | LSDMR_ACTTORW3 \ 178 | LSDMR_BL8 \ 179 | LSDMR_WRC2 \ 180 | LSDMR_CL3 \ 181 | LSDMR_RFEN \ 182 ) 183 184 /* 185 * SDRAM Controller configuration sequence. 186 */ 187 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 188 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 189 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 190 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 191 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 192 193 /* 194 * 32KB, 8-bit wide for ADS config reg 195 */ 196 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 197 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 198 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 199 200 #define CONFIG_SYS_INIT_RAM_LOCK 1 201 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 202 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 203 204 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 205 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 206 207 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 208 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 209 210 /* Serial Port */ 211 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 212 #undef CONFIG_CONS_NONE /* define if console on something else */ 213 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 214 215 #define CONFIG_BAUDRATE 115200 216 217 #define CONFIG_SYS_BAUDRATE_TABLE \ 218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 219 220 /* 221 * I2C 222 */ 223 #define CONFIG_SYS_I2C 224 #define CONFIG_SYS_I2C_FSL 225 #define CONFIG_SYS_FSL_I2C_SPEED 400000 226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 228 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 229 230 /* RapidIO MMU */ 231 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 232 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 233 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 234 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 235 236 /* 237 * General PCI 238 * Memory space is mapped 1-1, but I/O space must start from 0. 239 */ 240 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 241 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 242 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 243 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 244 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 245 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 246 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 247 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 248 249 #if defined(CONFIG_PCI) 250 #undef CONFIG_EEPRO100 251 #undef CONFIG_TULIP 252 253 #if !defined(CONFIG_PCI_PNP) 254 #define PCI_ENET0_IOADDR 0xe0000000 255 #define PCI_ENET0_MEMADDR 0xe0000000 256 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 257 #endif 258 259 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 260 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 261 262 #endif /* CONFIG_PCI */ 263 264 #ifdef CONFIG_TSEC_ENET 265 266 #ifndef CONFIG_MII 267 #define CONFIG_MII 1 /* MII PHY management */ 268 #endif 269 #define CONFIG_TSEC1 1 270 #define CONFIG_TSEC1_NAME "TSEC0" 271 #define CONFIG_TSEC2 1 272 #define CONFIG_TSEC2_NAME "TSEC1" 273 #define TSEC1_PHY_ADDR 0 274 #define TSEC2_PHY_ADDR 1 275 #define TSEC1_PHYIDX 0 276 #define TSEC2_PHYIDX 0 277 #define TSEC1_FLAGS TSEC_GIGABIT 278 #define TSEC2_FLAGS TSEC_GIGABIT 279 280 /* Options are: TSEC[0-1] */ 281 #define CONFIG_ETHPRIME "TSEC0" 282 283 #endif /* CONFIG_TSEC_ENET */ 284 285 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 286 287 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 288 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 289 290 #if (CONFIG_ETHER_INDEX == 2) 291 /* 292 * - Rx-CLK is CLK13 293 * - Tx-CLK is CLK14 294 * - Select bus for bd/buffers 295 * - Full duplex 296 */ 297 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 298 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 299 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 300 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 301 #define FETH2_RST 0x01 302 #elif (CONFIG_ETHER_INDEX == 3) 303 /* need more definitions here for FE3 */ 304 #define FETH3_RST 0x80 305 #endif /* CONFIG_ETHER_INDEX */ 306 307 #ifndef CONFIG_MII 308 #define CONFIG_MII 1 /* MII PHY management */ 309 #endif 310 311 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 312 313 /* 314 * GPIO pins used for bit-banged MII communications 315 */ 316 #define MDIO_PORT 2 /* Port C */ 317 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 318 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 319 #define MDC_DECLARE MDIO_DECLARE 320 321 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 322 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 323 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 324 325 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 326 else iop->pdat &= ~0x00400000 327 328 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 329 else iop->pdat &= ~0x00200000 330 331 #define MIIDELAY udelay(1) 332 333 #endif 334 335 /* 336 * Environment 337 */ 338 #ifndef CONFIG_SYS_RAMBOOT 339 #define CONFIG_ENV_IS_IN_FLASH 1 340 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 341 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 342 #define CONFIG_ENV_SIZE 0x2000 343 #else 344 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 345 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 346 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 347 #define CONFIG_ENV_SIZE 0x2000 348 #endif 349 350 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 351 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 352 353 /* 354 * BOOTP options 355 */ 356 #define CONFIG_BOOTP_BOOTFILESIZE 357 #define CONFIG_BOOTP_BOOTPATH 358 #define CONFIG_BOOTP_GATEWAY 359 #define CONFIG_BOOTP_HOSTNAME 360 361 /* 362 * Command line configuration. 363 */ 364 #define CONFIG_CMD_IRQ 365 #define CONFIG_CMD_REGINFO 366 367 #if defined(CONFIG_PCI) 368 #define CONFIG_CMD_PCI 369 #endif 370 371 #if defined(CONFIG_ETHER_ON_FCC) 372 #endif 373 374 #undef CONFIG_WATCHDOG /* watchdog disabled */ 375 376 /* 377 * Miscellaneous configurable options 378 */ 379 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 380 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 381 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 382 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 383 384 #if defined(CONFIG_CMD_KGDB) 385 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 386 #else 387 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 388 #endif 389 390 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 391 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 392 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 393 394 /* 395 * For booting Linux, the board info and command line data 396 * have to be in the first 64 MB of memory, since this is 397 * the maximum mapped by the Linux kernel during initialization. 398 */ 399 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 400 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 401 402 #if defined(CONFIG_CMD_KGDB) 403 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 404 #endif 405 406 /* 407 * Environment Configuration 408 */ 409 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 410 #define CONFIG_HAS_ETH0 411 #define CONFIG_HAS_ETH1 412 #define CONFIG_HAS_ETH2 413 #define CONFIG_HAS_ETH3 414 #endif 415 416 #define CONFIG_IPADDR 192.168.1.253 417 418 #define CONFIG_HOSTNAME unknown 419 #define CONFIG_ROOTPATH "/nfsroot" 420 #define CONFIG_BOOTFILE "your.uImage" 421 422 #define CONFIG_SERVERIP 192.168.1.1 423 #define CONFIG_GATEWAYIP 192.168.1.1 424 #define CONFIG_NETMASK 255.255.255.0 425 426 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 427 428 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 429 430 #define CONFIG_BAUDRATE 115200 431 432 #define CONFIG_EXTRA_ENV_SETTINGS \ 433 "netdev=eth0\0" \ 434 "consoledev=ttyCPM\0" \ 435 "ramdiskaddr=1000000\0" \ 436 "ramdiskfile=your.ramdisk.u-boot\0" \ 437 "fdtaddr=400000\0" \ 438 "fdtfile=mpc8560ads.dtb\0" 439 440 #define CONFIG_NFSBOOTCOMMAND \ 441 "setenv bootargs root=/dev/nfs rw " \ 442 "nfsroot=$serverip:$rootpath " \ 443 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 444 "console=$consoledev,$baudrate $othbootargs;" \ 445 "tftp $loadaddr $bootfile;" \ 446 "tftp $fdtaddr $fdtfile;" \ 447 "bootm $loadaddr - $fdtaddr" 448 449 #define CONFIG_RAMBOOTCOMMAND \ 450 "setenv bootargs root=/dev/ram rw " \ 451 "console=$consoledev,$baudrate $othbootargs;" \ 452 "tftp $ramdiskaddr $ramdiskfile;" \ 453 "tftp $loadaddr $bootfile;" \ 454 "tftp $fdtaddr $fdtfile;" \ 455 "bootm $loadaddr $ramdiskaddr $fdtaddr" 456 457 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 458 459 #endif /* __CONFIG_H */ 460