1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_CPM2 1 /* has CPM2 */ 23 24 /* 25 * default CCARBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0xfff80000 29 30 #define CONFIG_PCI_INDIRECT_BRIDGE 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 33 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 34 #define CONFIG_ENV_OVERWRITE 35 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 36 37 /* 38 * sysclk for MPC85xx 39 * 40 * Two valid values are: 41 * 33000000 42 * 66000000 43 * 44 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 45 * is likely the desired value here, so that is now the default. 46 * The board, however, can run at 66MHz. In any event, this value 47 * must match the settings of some switches. Details can be found 48 * in the README.mpc85xxads. 49 */ 50 51 #ifndef CONFIG_SYS_CLK_FREQ 52 #define CONFIG_SYS_CLK_FREQ 33000000 53 #endif 54 55 /* 56 * These can be toggled for performance analysis, otherwise use default. 57 */ 58 #define CONFIG_L2_CACHE /* toggle L2 cache */ 59 #define CONFIG_BTB /* toggle branch predition */ 60 61 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 62 63 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 64 #define CONFIG_SYS_MEMTEST_END 0x00400000 65 66 #define CONFIG_SYS_CCSRBAR 0xe0000000 67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 68 69 /* DDR Setup */ 70 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 71 #define CONFIG_DDR_SPD 72 #undef CONFIG_FSL_DDR_INTERACTIVE 73 74 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 75 76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 78 79 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 80 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 81 82 /* I2C addresses of SPD EEPROMs */ 83 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 84 85 /* These are used when DDR doesn't use SPD. */ 86 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 87 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 88 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 89 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 90 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 91 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 92 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 93 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 94 95 /* 96 * SDRAM on the Local Bus 97 */ 98 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 99 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 100 101 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 102 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 103 104 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 105 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 106 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 107 #undef CONFIG_SYS_FLASH_CHECKSUM 108 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 109 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 110 111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 112 113 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 114 #define CONFIG_SYS_RAMBOOT 115 #else 116 #undef CONFIG_SYS_RAMBOOT 117 #endif 118 119 #define CONFIG_FLASH_CFI_DRIVER 120 #define CONFIG_SYS_FLASH_CFI 121 #define CONFIG_SYS_FLASH_EMPTY_INFO 122 123 #undef CONFIG_CLOCKS_IN_MHZ 124 125 /* 126 * Local Bus Definitions 127 */ 128 129 /* 130 * Base Register 2 and Option Register 2 configure SDRAM. 131 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 132 * 133 * For BR2, need: 134 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 135 * port-size = 32-bits = BR2[19:20] = 11 136 * no parity checking = BR2[21:22] = 00 137 * SDRAM for MSEL = BR2[24:26] = 011 138 * Valid = BR[31] = 1 139 * 140 * 0 4 8 12 16 20 24 28 141 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 142 * 143 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 144 * FIXME: the top 17 bits of BR2. 145 */ 146 147 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 148 149 /* 150 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 151 * 152 * For OR2, need: 153 * 64MB mask for AM, OR2[0:7] = 1111 1100 154 * XAM, OR2[17:18] = 11 155 * 9 columns OR2[19-21] = 010 156 * 13 rows OR2[23-25] = 100 157 * EAD set for extra time OR[31] = 1 158 * 159 * 0 4 8 12 16 20 24 28 160 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 161 */ 162 163 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 164 165 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 166 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 167 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 168 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 169 170 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 171 | LSDMR_RFCR5 \ 172 | LSDMR_PRETOACT3 \ 173 | LSDMR_ACTTORW3 \ 174 | LSDMR_BL8 \ 175 | LSDMR_WRC2 \ 176 | LSDMR_CL3 \ 177 | LSDMR_RFEN \ 178 ) 179 180 /* 181 * SDRAM Controller configuration sequence. 182 */ 183 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 184 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 185 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 186 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 187 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 188 189 /* 190 * 32KB, 8-bit wide for ADS config reg 191 */ 192 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 193 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 194 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 195 196 #define CONFIG_SYS_INIT_RAM_LOCK 1 197 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 198 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 199 200 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 202 203 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 204 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 205 206 /* Serial Port */ 207 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 208 #undef CONFIG_CONS_NONE /* define if console on something else */ 209 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 210 211 #define CONFIG_SYS_BAUDRATE_TABLE \ 212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 213 214 /* 215 * I2C 216 */ 217 #define CONFIG_SYS_I2C 218 #define CONFIG_SYS_I2C_FSL 219 #define CONFIG_SYS_FSL_I2C_SPEED 400000 220 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 221 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 222 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 223 224 /* RapidIO MMU */ 225 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 226 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 227 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 228 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 229 230 /* 231 * General PCI 232 * Memory space is mapped 1-1, but I/O space must start from 0. 233 */ 234 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 235 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 236 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 237 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 238 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 239 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 241 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 242 243 #if defined(CONFIG_PCI) 244 #undef CONFIG_EEPRO100 245 #undef CONFIG_TULIP 246 247 #if !defined(CONFIG_PCI_PNP) 248 #define PCI_ENET0_IOADDR 0xe0000000 249 #define PCI_ENET0_MEMADDR 0xe0000000 250 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 251 #endif 252 253 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 254 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 255 256 #endif /* CONFIG_PCI */ 257 258 #ifdef CONFIG_TSEC_ENET 259 260 #ifndef CONFIG_MII 261 #define CONFIG_MII 1 /* MII PHY management */ 262 #endif 263 #define CONFIG_TSEC1 1 264 #define CONFIG_TSEC1_NAME "TSEC0" 265 #define CONFIG_TSEC2 1 266 #define CONFIG_TSEC2_NAME "TSEC1" 267 #define TSEC1_PHY_ADDR 0 268 #define TSEC2_PHY_ADDR 1 269 #define TSEC1_PHYIDX 0 270 #define TSEC2_PHYIDX 0 271 #define TSEC1_FLAGS TSEC_GIGABIT 272 #define TSEC2_FLAGS TSEC_GIGABIT 273 274 /* Options are: TSEC[0-1] */ 275 #define CONFIG_ETHPRIME "TSEC0" 276 277 #endif /* CONFIG_TSEC_ENET */ 278 279 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 280 281 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 282 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 283 284 #if (CONFIG_ETHER_INDEX == 2) 285 /* 286 * - Rx-CLK is CLK13 287 * - Tx-CLK is CLK14 288 * - Select bus for bd/buffers 289 * - Full duplex 290 */ 291 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 292 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 293 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 294 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 295 #define FETH2_RST 0x01 296 #elif (CONFIG_ETHER_INDEX == 3) 297 /* need more definitions here for FE3 */ 298 #define FETH3_RST 0x80 299 #endif /* CONFIG_ETHER_INDEX */ 300 301 #ifndef CONFIG_MII 302 #define CONFIG_MII 1 /* MII PHY management */ 303 #endif 304 305 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 306 307 /* 308 * GPIO pins used for bit-banged MII communications 309 */ 310 #define MDIO_PORT 2 /* Port C */ 311 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 312 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 313 #define MDC_DECLARE MDIO_DECLARE 314 315 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 316 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 317 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 318 319 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 320 else iop->pdat &= ~0x00400000 321 322 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 323 else iop->pdat &= ~0x00200000 324 325 #define MIIDELAY udelay(1) 326 327 #endif 328 329 /* 330 * Environment 331 */ 332 #ifndef CONFIG_SYS_RAMBOOT 333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 334 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 335 #define CONFIG_ENV_SIZE 0x2000 336 #else 337 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 338 #define CONFIG_ENV_SIZE 0x2000 339 #endif 340 341 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 342 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 343 344 /* 345 * BOOTP options 346 */ 347 #define CONFIG_BOOTP_BOOTFILESIZE 348 #define CONFIG_BOOTP_BOOTPATH 349 #define CONFIG_BOOTP_GATEWAY 350 #define CONFIG_BOOTP_HOSTNAME 351 352 #undef CONFIG_WATCHDOG /* watchdog disabled */ 353 354 /* 355 * Miscellaneous configurable options 356 */ 357 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 358 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 359 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 360 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 361 362 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 363 364 /* 365 * For booting Linux, the board info and command line data 366 * have to be in the first 64 MB of memory, since this is 367 * the maximum mapped by the Linux kernel during initialization. 368 */ 369 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 370 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 371 372 #if defined(CONFIG_CMD_KGDB) 373 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 374 #endif 375 376 /* 377 * Environment Configuration 378 */ 379 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 380 #define CONFIG_HAS_ETH0 381 #define CONFIG_HAS_ETH1 382 #define CONFIG_HAS_ETH2 383 #define CONFIG_HAS_ETH3 384 #endif 385 386 #define CONFIG_IPADDR 192.168.1.253 387 388 #define CONFIG_HOSTNAME unknown 389 #define CONFIG_ROOTPATH "/nfsroot" 390 #define CONFIG_BOOTFILE "your.uImage" 391 392 #define CONFIG_SERVERIP 192.168.1.1 393 #define CONFIG_GATEWAYIP 192.168.1.1 394 #define CONFIG_NETMASK 255.255.255.0 395 396 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 397 398 #define CONFIG_EXTRA_ENV_SETTINGS \ 399 "netdev=eth0\0" \ 400 "consoledev=ttyCPM\0" \ 401 "ramdiskaddr=1000000\0" \ 402 "ramdiskfile=your.ramdisk.u-boot\0" \ 403 "fdtaddr=400000\0" \ 404 "fdtfile=mpc8560ads.dtb\0" 405 406 #define CONFIG_NFSBOOTCOMMAND \ 407 "setenv bootargs root=/dev/nfs rw " \ 408 "nfsroot=$serverip:$rootpath " \ 409 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 410 "console=$consoledev,$baudrate $othbootargs;" \ 411 "tftp $loadaddr $bootfile;" \ 412 "tftp $fdtaddr $fdtfile;" \ 413 "bootm $loadaddr - $fdtaddr" 414 415 #define CONFIG_RAMBOOTCOMMAND \ 416 "setenv bootargs root=/dev/ram rw " \ 417 "console=$consoledev,$baudrate $othbootargs;" \ 418 "tftp $ramdiskaddr $ramdiskfile;" \ 419 "tftp $loadaddr $bootfile;" \ 420 "tftp $fdtaddr $fdtfile;" \ 421 "bootm $loadaddr $ramdiskaddr $fdtaddr" 422 423 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 424 425 #endif /* __CONFIG_H */ 426