1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 * (C) Copyright 2002,2003 Motorola,Inc. 5 * Xianghua Xiao <X.Xiao@motorola.com> 6 */ 7 8 /* 9 * mpc8560ads board configuration file 10 * 11 * Please refer to doc/README.mpc85xx for more info. 12 * 13 * Make sure you change the MAC address and other network params first, 14 * search for CONFIG_SERVERIP, etc. in this file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* High Level Configuration Options */ 21 #define CONFIG_CPM2 1 /* has CPM2 */ 22 23 /* 24 * default CCARBAR is at 0xff700000 25 * assume U-Boot is less than 0.5MB 26 */ 27 28 #define CONFIG_PCI_INDIRECT_BRIDGE 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 31 #define CONFIG_ENV_OVERWRITE 32 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 33 34 /* 35 * sysclk for MPC85xx 36 * 37 * Two valid values are: 38 * 33000000 39 * 66000000 40 * 41 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 42 * is likely the desired value here, so that is now the default. 43 * The board, however, can run at 66MHz. In any event, this value 44 * must match the settings of some switches. Details can be found 45 * in the README.mpc85xxads. 46 */ 47 48 #ifndef CONFIG_SYS_CLK_FREQ 49 #define CONFIG_SYS_CLK_FREQ 33000000 50 #endif 51 52 /* 53 * These can be toggled for performance analysis, otherwise use default. 54 */ 55 #define CONFIG_L2_CACHE /* toggle L2 cache */ 56 #define CONFIG_BTB /* toggle branch predition */ 57 58 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 59 60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00400000 62 63 #define CONFIG_SYS_CCSRBAR 0xe0000000 64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 65 66 /* DDR Setup */ 67 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 68 #define CONFIG_DDR_SPD 69 #undef CONFIG_FSL_DDR_INTERACTIVE 70 71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 72 73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 75 76 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 77 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 78 79 /* I2C addresses of SPD EEPROMs */ 80 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 81 82 /* These are used when DDR doesn't use SPD. */ 83 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 84 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 85 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 86 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 87 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 88 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 89 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 90 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 91 92 /* 93 * SDRAM on the Local Bus 94 */ 95 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 96 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 97 98 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 99 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 100 101 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 102 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 103 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 104 #undef CONFIG_SYS_FLASH_CHECKSUM 105 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 106 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 107 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 109 110 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 111 #define CONFIG_SYS_RAMBOOT 112 #else 113 #undef CONFIG_SYS_RAMBOOT 114 #endif 115 116 #define CONFIG_SYS_FLASH_EMPTY_INFO 117 118 #undef CONFIG_CLOCKS_IN_MHZ 119 120 /* 121 * Local Bus Definitions 122 */ 123 124 /* 125 * Base Register 2 and Option Register 2 configure SDRAM. 126 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 127 * 128 * For BR2, need: 129 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 130 * port-size = 32-bits = BR2[19:20] = 11 131 * no parity checking = BR2[21:22] = 00 132 * SDRAM for MSEL = BR2[24:26] = 011 133 * Valid = BR[31] = 1 134 * 135 * 0 4 8 12 16 20 24 28 136 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 137 * 138 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 139 * FIXME: the top 17 bits of BR2. 140 */ 141 142 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 143 144 /* 145 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 146 * 147 * For OR2, need: 148 * 64MB mask for AM, OR2[0:7] = 1111 1100 149 * XAM, OR2[17:18] = 11 150 * 9 columns OR2[19-21] = 010 151 * 13 rows OR2[23-25] = 100 152 * EAD set for extra time OR[31] = 1 153 * 154 * 0 4 8 12 16 20 24 28 155 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 156 */ 157 158 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 159 160 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 161 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 162 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 163 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 164 165 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 166 | LSDMR_RFCR5 \ 167 | LSDMR_PRETOACT3 \ 168 | LSDMR_ACTTORW3 \ 169 | LSDMR_BL8 \ 170 | LSDMR_WRC2 \ 171 | LSDMR_CL3 \ 172 | LSDMR_RFEN \ 173 ) 174 175 /* 176 * SDRAM Controller configuration sequence. 177 */ 178 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 179 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 180 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 181 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 182 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 183 184 /* 185 * 32KB, 8-bit wide for ADS config reg 186 */ 187 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 188 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 189 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 190 191 #define CONFIG_SYS_INIT_RAM_LOCK 1 192 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 193 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 194 195 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 196 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 197 198 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 199 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 200 201 /* Serial Port */ 202 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 203 #undef CONFIG_CONS_NONE /* define if console on something else */ 204 205 #define CONFIG_SYS_BAUDRATE_TABLE \ 206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 207 208 /* 209 * I2C 210 */ 211 #define CONFIG_SYS_I2C 212 #define CONFIG_SYS_I2C_FSL 213 #define CONFIG_SYS_FSL_I2C_SPEED 400000 214 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 216 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 217 218 /* RapidIO MMU */ 219 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 220 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 221 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 222 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 223 224 /* 225 * General PCI 226 * Memory space is mapped 1-1, but I/O space must start from 0. 227 */ 228 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 229 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 230 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 231 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 232 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 233 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 234 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 235 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 236 237 #if defined(CONFIG_PCI) 238 #undef CONFIG_EEPRO100 239 #undef CONFIG_TULIP 240 241 #if !defined(CONFIG_PCI_PNP) 242 #define PCI_ENET0_IOADDR 0xe0000000 243 #define PCI_ENET0_MEMADDR 0xe0000000 244 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 245 #endif 246 247 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 248 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 249 250 #endif /* CONFIG_PCI */ 251 252 #ifdef CONFIG_TSEC_ENET 253 254 #define CONFIG_TSEC1 1 255 #define CONFIG_TSEC1_NAME "TSEC0" 256 #define CONFIG_TSEC2 1 257 #define CONFIG_TSEC2_NAME "TSEC1" 258 #define TSEC1_PHY_ADDR 0 259 #define TSEC2_PHY_ADDR 1 260 #define TSEC1_PHYIDX 0 261 #define TSEC2_PHYIDX 0 262 #define TSEC1_FLAGS TSEC_GIGABIT 263 #define TSEC2_FLAGS TSEC_GIGABIT 264 265 /* Options are: TSEC[0-1] */ 266 #define CONFIG_ETHPRIME "TSEC0" 267 268 #endif /* CONFIG_TSEC_ENET */ 269 270 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 271 272 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 273 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 274 275 #if (CONFIG_ETHER_INDEX == 2) 276 /* 277 * - Rx-CLK is CLK13 278 * - Tx-CLK is CLK14 279 * - Select bus for bd/buffers 280 * - Full duplex 281 */ 282 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 283 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 284 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 285 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 286 #define FETH2_RST 0x01 287 #elif (CONFIG_ETHER_INDEX == 3) 288 /* need more definitions here for FE3 */ 289 #define FETH3_RST 0x80 290 #endif /* CONFIG_ETHER_INDEX */ 291 292 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 293 294 /* 295 * GPIO pins used for bit-banged MII communications 296 */ 297 #define MDIO_PORT 2 /* Port C */ 298 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 299 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 300 #define MDC_DECLARE MDIO_DECLARE 301 302 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 303 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 304 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 305 306 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 307 else iop->pdat &= ~0x00400000 308 309 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 310 else iop->pdat &= ~0x00200000 311 312 #define MIIDELAY udelay(1) 313 314 #endif 315 316 /* 317 * Environment 318 */ 319 #ifndef CONFIG_SYS_RAMBOOT 320 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 321 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 322 #define CONFIG_ENV_SIZE 0x2000 323 #else 324 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 325 #define CONFIG_ENV_SIZE 0x2000 326 #endif 327 328 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 329 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 330 331 /* 332 * BOOTP options 333 */ 334 #define CONFIG_BOOTP_BOOTFILESIZE 335 336 #undef CONFIG_WATCHDOG /* watchdog disabled */ 337 338 /* 339 * Miscellaneous configurable options 340 */ 341 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 342 343 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 344 345 /* 346 * For booting Linux, the board info and command line data 347 * have to be in the first 64 MB of memory, since this is 348 * the maximum mapped by the Linux kernel during initialization. 349 */ 350 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 351 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 352 353 #if defined(CONFIG_CMD_KGDB) 354 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 355 #endif 356 357 /* 358 * Environment Configuration 359 */ 360 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 361 #define CONFIG_HAS_ETH0 362 #define CONFIG_HAS_ETH1 363 #define CONFIG_HAS_ETH2 364 #define CONFIG_HAS_ETH3 365 #endif 366 367 #define CONFIG_IPADDR 192.168.1.253 368 369 #define CONFIG_HOSTNAME "unknown" 370 #define CONFIG_ROOTPATH "/nfsroot" 371 #define CONFIG_BOOTFILE "your.uImage" 372 373 #define CONFIG_SERVERIP 192.168.1.1 374 #define CONFIG_GATEWAYIP 192.168.1.1 375 #define CONFIG_NETMASK 255.255.255.0 376 377 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 378 379 #define CONFIG_EXTRA_ENV_SETTINGS \ 380 "netdev=eth0\0" \ 381 "consoledev=ttyCPM\0" \ 382 "ramdiskaddr=1000000\0" \ 383 "ramdiskfile=your.ramdisk.u-boot\0" \ 384 "fdtaddr=400000\0" \ 385 "fdtfile=mpc8560ads.dtb\0" 386 387 #define CONFIG_NFSBOOTCOMMAND \ 388 "setenv bootargs root=/dev/nfs rw " \ 389 "nfsroot=$serverip:$rootpath " \ 390 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 391 "console=$consoledev,$baudrate $othbootargs;" \ 392 "tftp $loadaddr $bootfile;" \ 393 "tftp $fdtaddr $fdtfile;" \ 394 "bootm $loadaddr - $fdtaddr" 395 396 #define CONFIG_RAMBOOTCOMMAND \ 397 "setenv bootargs root=/dev/ram rw " \ 398 "console=$consoledev,$baudrate $othbootargs;" \ 399 "tftp $ramdiskaddr $ramdiskfile;" \ 400 "tftp $loadaddr $bootfile;" \ 401 "tftp $fdtaddr $fdtfile;" \ 402 "bootm $loadaddr $ramdiskaddr $fdtaddr" 403 404 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 405 406 #endif /* __CONFIG_H */ 407