1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8560ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_CPM2 1 /* has CPM2 */ 42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 43 44 #define CONFIG_PCI 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 49 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 50 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 51 52 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 54 55 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 56 57 /* 58 * sysclk for MPC85xx 59 * 60 * Two valid values are: 61 * 33000000 62 * 66000000 63 * 64 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 65 * is likely the desired value here, so that is now the default. 66 * The board, however, can run at 66MHz. In any event, this value 67 * must match the settings of some switches. Details can be found 68 * in the README.mpc85xxads. 69 */ 70 71 #ifndef CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_CLK_FREQ 33000000 73 #endif 74 75 76 /* 77 * These can be toggled for performance analysis, otherwise use default. 78 */ 79 #define CONFIG_L2_CACHE /* toggle L2 cache */ 80 #define CONFIG_BTB /* toggle branch predition */ 81 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 82 83 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 84 85 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 86 87 #undef CFG_DRAM_TEST /* memory test, takes time */ 88 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 89 #define CFG_MEMTEST_END 0x00400000 90 91 92 /* 93 * Base addresses -- Note these are effective addresses where the 94 * actual resources get mapped (not physical addresses) 95 */ 96 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 97 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 98 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 99 100 101 /* 102 * DDR Setup 103 */ 104 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 105 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 106 107 #if defined(CONFIG_SPD_EEPROM) 108 /* 109 * Determine DDR configuration from I2C interface. 110 */ 111 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 112 113 #else 114 /* 115 * Manually set up DDR parameters 116 */ 117 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 118 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 119 #define CFG_DDR_CS0_CONFIG 0x80000002 120 #define CFG_DDR_TIMING_1 0x37344321 121 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 122 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 123 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 124 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 125 #endif 126 127 128 /* 129 * SDRAM on the Local Bus 130 */ 131 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 132 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 133 134 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 135 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 136 137 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 138 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 139 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 140 #undef CFG_FLASH_CHECKSUM 141 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 142 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 143 144 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 145 146 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 147 #define CFG_RAMBOOT 148 #else 149 #undef CFG_RAMBOOT 150 #endif 151 152 #define CFG_FLASH_CFI_DRIVER 153 #define CFG_FLASH_CFI 154 #define CFG_FLASH_EMPTY_INFO 155 156 #undef CONFIG_CLOCKS_IN_MHZ 157 158 159 /* 160 * Local Bus Definitions 161 */ 162 163 /* 164 * Base Register 2 and Option Register 2 configure SDRAM. 165 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 166 * 167 * For BR2, need: 168 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 169 * port-size = 32-bits = BR2[19:20] = 11 170 * no parity checking = BR2[21:22] = 00 171 * SDRAM for MSEL = BR2[24:26] = 011 172 * Valid = BR[31] = 1 173 * 174 * 0 4 8 12 16 20 24 28 175 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 176 * 177 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 178 * FIXME: the top 17 bits of BR2. 179 */ 180 181 #define CFG_BR2_PRELIM 0xf0001861 182 183 /* 184 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 185 * 186 * For OR2, need: 187 * 64MB mask for AM, OR2[0:7] = 1111 1100 188 * XAM, OR2[17:18] = 11 189 * 9 columns OR2[19-21] = 010 190 * 13 rows OR2[23-25] = 100 191 * EAD set for extra time OR[31] = 1 192 * 193 * 0 4 8 12 16 20 24 28 194 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 195 */ 196 197 #define CFG_OR2_PRELIM 0xfc006901 198 199 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 200 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 201 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 202 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 203 204 /* 205 * LSDMR masks 206 */ 207 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 208 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 209 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 210 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 211 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 212 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 213 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 214 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 215 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 216 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 217 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 218 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 219 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 220 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 221 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 222 223 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 231 232 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 233 | CFG_LBC_LSDMR_RFCR5 \ 234 | CFG_LBC_LSDMR_PRETOACT3 \ 235 | CFG_LBC_LSDMR_ACTTORW3 \ 236 | CFG_LBC_LSDMR_BL8 \ 237 | CFG_LBC_LSDMR_WRC2 \ 238 | CFG_LBC_LSDMR_CL3 \ 239 | CFG_LBC_LSDMR_RFEN \ 240 ) 241 242 /* 243 * SDRAM Controller configuration sequence. 244 */ 245 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 246 | CFG_LBC_LSDMR_OP_PCHALL) 247 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 248 | CFG_LBC_LSDMR_OP_ARFRSH) 249 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 250 | CFG_LBC_LSDMR_OP_ARFRSH) 251 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 252 | CFG_LBC_LSDMR_OP_MRW) 253 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 254 | CFG_LBC_LSDMR_OP_NORMAL) 255 256 257 /* 258 * 32KB, 8-bit wide for ADS config reg 259 */ 260 #define CFG_BR4_PRELIM 0xf8000801 261 #define CFG_OR4_PRELIM 0xffffe1f1 262 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 263 264 #define CONFIG_L1_INIT_RAM 265 #define CFG_INIT_RAM_LOCK 1 266 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 267 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 268 269 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 270 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 271 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 272 273 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 274 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 275 276 /* Serial Port */ 277 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 278 #undef CONFIG_CONS_NONE /* define if console on something else */ 279 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 280 281 #define CONFIG_BAUDRATE 115200 282 283 #define CFG_BAUDRATE_TABLE \ 284 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 285 286 /* Use the HUSH parser */ 287 #define CFG_HUSH_PARSER 288 #ifdef CFG_HUSH_PARSER 289 #define CFG_PROMPT_HUSH_PS2 "> " 290 #endif 291 292 /* pass open firmware flat tree */ 293 #define CONFIG_OF_LIBFDT 1 294 #define CONFIG_OF_BOARD_SETUP 1 295 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 296 297 /* 298 * I2C 299 */ 300 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 301 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 302 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 303 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 304 #define CFG_I2C_SLAVE 0x7F 305 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 306 #define CFG_I2C_OFFSET 0x3000 307 308 /* RapidIO MMU */ 309 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 310 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 311 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 312 313 /* 314 * General PCI 315 * Memory space is mapped 1-1, but I/O space must start from 0. 316 */ 317 #define CFG_PCI1_MEM_BASE 0x80000000 318 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 319 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 320 #define CFG_PCI1_IO_BASE 0x00000000 321 #define CFG_PCI1_IO_PHYS 0xe2000000 322 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ 323 324 #if defined(CONFIG_PCI) 325 326 #define CONFIG_NET_MULTI 327 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 328 329 #undef CONFIG_EEPRO100 330 #undef CONFIG_TULIP 331 332 #if !defined(CONFIG_PCI_PNP) 333 #define PCI_ENET0_IOADDR 0xe0000000 334 #define PCI_ENET0_MEMADDR 0xe0000000 335 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 336 #endif 337 338 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 339 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 340 341 #endif /* CONFIG_PCI */ 342 343 344 #ifdef CONFIG_TSEC_ENET 345 346 #ifndef CONFIG_NET_MULTI 347 #define CONFIG_NET_MULTI 1 348 #endif 349 350 #ifndef CONFIG_MII 351 #define CONFIG_MII 1 /* MII PHY management */ 352 #endif 353 #define CONFIG_TSEC1 1 354 #define CONFIG_TSEC1_NAME "TSEC0" 355 #define CONFIG_TSEC2 1 356 #define CONFIG_TSEC2_NAME "TSEC1" 357 #define TSEC1_PHY_ADDR 0 358 #define TSEC2_PHY_ADDR 1 359 #define TSEC1_PHYIDX 0 360 #define TSEC2_PHYIDX 0 361 #define TSEC1_FLAGS TSEC_GIGABIT 362 #define TSEC2_FLAGS TSEC_GIGABIT 363 364 /* Options are: TSEC[0-1] */ 365 #define CONFIG_ETHPRIME "TSEC0" 366 367 #endif /* CONFIG_TSEC_ENET */ 368 369 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 370 371 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 372 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 373 374 #if (CONFIG_ETHER_INDEX == 2) 375 /* 376 * - Rx-CLK is CLK13 377 * - Tx-CLK is CLK14 378 * - Select bus for bd/buffers 379 * - Full duplex 380 */ 381 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 382 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 383 #define CFG_CPMFCR_RAMTYPE 0 384 #define CFG_FCC_PSMR (FCC_PSMR_FDE) 385 #define FETH2_RST 0x01 386 #elif (CONFIG_ETHER_INDEX == 3) 387 /* need more definitions here for FE3 */ 388 #define FETH3_RST 0x80 389 #endif /* CONFIG_ETHER_INDEX */ 390 391 #ifndef CONFIG_MII 392 #define CONFIG_MII 1 /* MII PHY management */ 393 #endif 394 395 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 396 397 /* 398 * GPIO pins used for bit-banged MII communications 399 */ 400 #define MDIO_PORT 2 /* Port C */ 401 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 402 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 403 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 404 405 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 406 else iop->pdat &= ~0x00400000 407 408 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 409 else iop->pdat &= ~0x00200000 410 411 #define MIIDELAY udelay(1) 412 413 #endif 414 415 416 /* 417 * Environment 418 */ 419 #ifndef CFG_RAMBOOT 420 #define CFG_ENV_IS_IN_FLASH 1 421 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 422 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 423 #define CFG_ENV_SIZE 0x2000 424 #else 425 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 426 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 427 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 428 #define CFG_ENV_SIZE 0x2000 429 #endif 430 431 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 432 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 433 434 /* 435 * BOOTP options 436 */ 437 #define CONFIG_BOOTP_BOOTFILESIZE 438 #define CONFIG_BOOTP_BOOTPATH 439 #define CONFIG_BOOTP_GATEWAY 440 #define CONFIG_BOOTP_HOSTNAME 441 442 443 /* 444 * Command line configuration. 445 */ 446 #include <config_cmd_default.h> 447 448 #define CONFIG_CMD_PING 449 #define CONFIG_CMD_I2C 450 #define CONFIG_CMD_ELF 451 452 #if defined(CONFIG_PCI) 453 #define CONFIG_CMD_PCI 454 #endif 455 456 #if defined(CONFIG_ETHER_ON_FCC) 457 #define CONFIG_CMD_MII 458 #endif 459 460 #if defined(CFG_RAMBOOT) 461 #undef CONFIG_CMD_ENV 462 #undef CONFIG_CMD_LOADS 463 #endif 464 465 466 #undef CONFIG_WATCHDOG /* watchdog disabled */ 467 468 /* 469 * Miscellaneous configurable options 470 */ 471 #define CFG_LONGHELP /* undef to save memory */ 472 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 473 #define CFG_LOAD_ADDR 0x1000000 /* default load address */ 474 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 475 476 #if defined(CONFIG_CMD_KGDB) 477 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 478 #else 479 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 480 #endif 481 482 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 483 #define CFG_MAXARGS 16 /* max number of command args */ 484 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 485 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 486 487 /* 488 * For booting Linux, the board info and command line data 489 * have to be in the first 8 MB of memory, since this is 490 * the maximum mapped by the Linux kernel during initialization. 491 */ 492 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 493 494 /* 495 * Internal Definitions 496 * 497 * Boot Flags 498 */ 499 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 500 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 501 502 #if defined(CONFIG_CMD_KGDB) 503 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 504 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 505 #endif 506 507 508 /* 509 * Environment Configuration 510 */ 511 512 /* The mac addresses for all ethernet interface */ 513 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 514 #define CONFIG_HAS_ETH0 515 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 516 #define CONFIG_HAS_ETH1 517 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 518 #define CONFIG_HAS_ETH2 519 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 520 #define CONFIG_HAS_ETH3 521 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 522 #endif 523 524 #define CONFIG_IPADDR 192.168.1.253 525 526 #define CONFIG_HOSTNAME unknown 527 #define CONFIG_ROOTPATH /nfsroot 528 #define CONFIG_BOOTFILE your.uImage 529 530 #define CONFIG_SERVERIP 192.168.1.1 531 #define CONFIG_GATEWAYIP 192.168.1.1 532 #define CONFIG_NETMASK 255.255.255.0 533 534 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 535 536 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 537 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 538 539 #define CONFIG_BAUDRATE 115200 540 541 #define CONFIG_EXTRA_ENV_SETTINGS \ 542 "netdev=eth0\0" \ 543 "consoledev=ttyCPM\0" \ 544 "ramdiskaddr=1000000\0" \ 545 "ramdiskfile=your.ramdisk.u-boot\0" \ 546 "fdtaddr=400000\0" \ 547 "fdtfile=mpc8560ads.dtb\0" 548 549 #define CONFIG_NFSBOOTCOMMAND \ 550 "setenv bootargs root=/dev/nfs rw " \ 551 "nfsroot=$serverip:$rootpath " \ 552 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 553 "console=$consoledev,$baudrate $othbootargs;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "tftp $fdtaddr $fdtfile;" \ 556 "bootm $loadaddr - $fdtaddr" 557 558 #define CONFIG_RAMBOOTCOMMAND \ 559 "setenv bootargs root=/dev/ram rw " \ 560 "console=$consoledev,$baudrate $othbootargs;" \ 561 "tftp $ramdiskaddr $ramdiskfile;" \ 562 "tftp $loadaddr $bootfile;" \ 563 "tftp $fdtaddr $fdtfile;" \ 564 "bootm $loadaddr $ramdiskaddr $fdtaddr" 565 566 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 567 568 #endif /* __CONFIG_H */ 569