1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 #define CONFIG_DISPLAY_BOARDINFO 22 23 /* High Level Configuration Options */ 24 #define CONFIG_BOOKE 1 /* BOOKE */ 25 #define CONFIG_E500 1 /* BOOKE e500 family */ 26 #define CONFIG_CPM2 1 /* has CPM2 */ 27 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 28 #define CONFIG_MPC8560 1 29 30 /* 31 * default CCARBAR is at 0xff700000 32 * assume U-Boot is less than 0.5MB 33 */ 34 #define CONFIG_SYS_TEXT_BASE 0xfff80000 35 36 #define CONFIG_PCI 37 #define CONFIG_PCI_INDIRECT_BRIDGE 38 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 39 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 40 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 41 #define CONFIG_ENV_OVERWRITE 42 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 43 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 44 45 /* 46 * sysclk for MPC85xx 47 * 48 * Two valid values are: 49 * 33000000 50 * 66000000 51 * 52 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 53 * is likely the desired value here, so that is now the default. 54 * The board, however, can run at 66MHz. In any event, this value 55 * must match the settings of some switches. Details can be found 56 * in the README.mpc85xxads. 57 */ 58 59 #ifndef CONFIG_SYS_CLK_FREQ 60 #define CONFIG_SYS_CLK_FREQ 33000000 61 #endif 62 63 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE /* toggle L2 cache */ 68 #define CONFIG_BTB /* toggle branch predition */ 69 70 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 73 #define CONFIG_SYS_MEMTEST_END 0x00400000 74 75 #define CONFIG_SYS_CCSRBAR 0xe0000000 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77 78 /* DDR Setup */ 79 #define CONFIG_SYS_FSL_DDR1 80 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 81 #define CONFIG_DDR_SPD 82 #undef CONFIG_FSL_DDR_INTERACTIVE 83 84 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 85 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_NUM_DDR_CONTROLLERS 1 90 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 91 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 92 93 /* I2C addresses of SPD EEPROMs */ 94 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 95 96 /* These are used when DDR doesn't use SPD. */ 97 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 98 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 99 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 100 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 101 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 102 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 103 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 104 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 105 106 /* 107 * SDRAM on the Local Bus 108 */ 109 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 110 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 111 112 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 113 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 114 115 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 116 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 117 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 118 #undef CONFIG_SYS_FLASH_CHECKSUM 119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 121 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 123 124 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 125 #define CONFIG_SYS_RAMBOOT 126 #else 127 #undef CONFIG_SYS_RAMBOOT 128 #endif 129 130 #define CONFIG_FLASH_CFI_DRIVER 131 #define CONFIG_SYS_FLASH_CFI 132 #define CONFIG_SYS_FLASH_EMPTY_INFO 133 134 #undef CONFIG_CLOCKS_IN_MHZ 135 136 137 /* 138 * Local Bus Definitions 139 */ 140 141 /* 142 * Base Register 2 and Option Register 2 configure SDRAM. 143 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 144 * 145 * For BR2, need: 146 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 147 * port-size = 32-bits = BR2[19:20] = 11 148 * no parity checking = BR2[21:22] = 00 149 * SDRAM for MSEL = BR2[24:26] = 011 150 * Valid = BR[31] = 1 151 * 152 * 0 4 8 12 16 20 24 28 153 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 154 * 155 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 156 * FIXME: the top 17 bits of BR2. 157 */ 158 159 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 160 161 /* 162 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 163 * 164 * For OR2, need: 165 * 64MB mask for AM, OR2[0:7] = 1111 1100 166 * XAM, OR2[17:18] = 11 167 * 9 columns OR2[19-21] = 010 168 * 13 rows OR2[23-25] = 100 169 * EAD set for extra time OR[31] = 1 170 * 171 * 0 4 8 12 16 20 24 28 172 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 173 */ 174 175 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 176 177 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 178 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 179 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 180 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 181 182 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 183 | LSDMR_RFCR5 \ 184 | LSDMR_PRETOACT3 \ 185 | LSDMR_ACTTORW3 \ 186 | LSDMR_BL8 \ 187 | LSDMR_WRC2 \ 188 | LSDMR_CL3 \ 189 | LSDMR_RFEN \ 190 ) 191 192 /* 193 * SDRAM Controller configuration sequence. 194 */ 195 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 196 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 197 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 198 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 199 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 200 201 202 /* 203 * 32KB, 8-bit wide for ADS config reg 204 */ 205 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 206 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 207 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 208 209 #define CONFIG_SYS_INIT_RAM_LOCK 1 210 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 211 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 212 213 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 214 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 215 216 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 217 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 218 219 /* Serial Port */ 220 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 221 #undef CONFIG_CONS_NONE /* define if console on something else */ 222 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 223 224 #define CONFIG_BAUDRATE 115200 225 226 #define CONFIG_SYS_BAUDRATE_TABLE \ 227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 228 229 /* Use the HUSH parser */ 230 #define CONFIG_SYS_HUSH_PARSER 231 #ifdef CONFIG_SYS_HUSH_PARSER 232 #endif 233 234 /* 235 * I2C 236 */ 237 #define CONFIG_SYS_I2C 238 #define CONFIG_SYS_I2C_FSL 239 #define CONFIG_SYS_FSL_I2C_SPEED 400000 240 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 241 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 242 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 243 244 /* RapidIO MMU */ 245 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 246 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 247 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 248 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 249 250 /* 251 * General PCI 252 * Memory space is mapped 1-1, but I/O space must start from 0. 253 */ 254 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 255 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 256 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 257 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 258 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 259 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 260 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 261 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 262 263 #if defined(CONFIG_PCI) 264 265 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 266 267 #undef CONFIG_EEPRO100 268 #undef CONFIG_TULIP 269 270 #if !defined(CONFIG_PCI_PNP) 271 #define PCI_ENET0_IOADDR 0xe0000000 272 #define PCI_ENET0_MEMADDR 0xe0000000 273 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 274 #endif 275 276 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 277 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 278 279 #endif /* CONFIG_PCI */ 280 281 282 #ifdef CONFIG_TSEC_ENET 283 284 #ifndef CONFIG_MII 285 #define CONFIG_MII 1 /* MII PHY management */ 286 #endif 287 #define CONFIG_TSEC1 1 288 #define CONFIG_TSEC1_NAME "TSEC0" 289 #define CONFIG_TSEC2 1 290 #define CONFIG_TSEC2_NAME "TSEC1" 291 #define TSEC1_PHY_ADDR 0 292 #define TSEC2_PHY_ADDR 1 293 #define TSEC1_PHYIDX 0 294 #define TSEC2_PHYIDX 0 295 #define TSEC1_FLAGS TSEC_GIGABIT 296 #define TSEC2_FLAGS TSEC_GIGABIT 297 298 /* Options are: TSEC[0-1] */ 299 #define CONFIG_ETHPRIME "TSEC0" 300 301 #endif /* CONFIG_TSEC_ENET */ 302 303 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 304 305 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 306 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 307 308 #if (CONFIG_ETHER_INDEX == 2) 309 /* 310 * - Rx-CLK is CLK13 311 * - Tx-CLK is CLK14 312 * - Select bus for bd/buffers 313 * - Full duplex 314 */ 315 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 316 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 317 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 318 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 319 #define FETH2_RST 0x01 320 #elif (CONFIG_ETHER_INDEX == 3) 321 /* need more definitions here for FE3 */ 322 #define FETH3_RST 0x80 323 #endif /* CONFIG_ETHER_INDEX */ 324 325 #ifndef CONFIG_MII 326 #define CONFIG_MII 1 /* MII PHY management */ 327 #endif 328 329 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 330 331 /* 332 * GPIO pins used for bit-banged MII communications 333 */ 334 #define MDIO_PORT 2 /* Port C */ 335 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 336 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 337 #define MDC_DECLARE MDIO_DECLARE 338 339 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 340 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 341 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 342 343 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 344 else iop->pdat &= ~0x00400000 345 346 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 347 else iop->pdat &= ~0x00200000 348 349 #define MIIDELAY udelay(1) 350 351 #endif 352 353 354 /* 355 * Environment 356 */ 357 #ifndef CONFIG_SYS_RAMBOOT 358 #define CONFIG_ENV_IS_IN_FLASH 1 359 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 360 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 361 #define CONFIG_ENV_SIZE 0x2000 362 #else 363 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 364 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 365 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 366 #define CONFIG_ENV_SIZE 0x2000 367 #endif 368 369 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 370 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 371 372 /* 373 * BOOTP options 374 */ 375 #define CONFIG_BOOTP_BOOTFILESIZE 376 #define CONFIG_BOOTP_BOOTPATH 377 #define CONFIG_BOOTP_GATEWAY 378 #define CONFIG_BOOTP_HOSTNAME 379 380 381 /* 382 * Command line configuration. 383 */ 384 #define CONFIG_CMD_PING 385 #define CONFIG_CMD_I2C 386 #define CONFIG_CMD_IRQ 387 #define CONFIG_CMD_REGINFO 388 389 #if defined(CONFIG_PCI) 390 #define CONFIG_CMD_PCI 391 #endif 392 393 #if defined(CONFIG_ETHER_ON_FCC) 394 #define CONFIG_CMD_MII 395 #endif 396 397 #undef CONFIG_WATCHDOG /* watchdog disabled */ 398 399 /* 400 * Miscellaneous configurable options 401 */ 402 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 403 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 404 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 405 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 406 407 #if defined(CONFIG_CMD_KGDB) 408 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 409 #else 410 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 411 #endif 412 413 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 414 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 415 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 416 417 /* 418 * For booting Linux, the board info and command line data 419 * have to be in the first 64 MB of memory, since this is 420 * the maximum mapped by the Linux kernel during initialization. 421 */ 422 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 423 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 424 425 #if defined(CONFIG_CMD_KGDB) 426 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 427 #endif 428 429 430 /* 431 * Environment Configuration 432 */ 433 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 434 #define CONFIG_HAS_ETH0 435 #define CONFIG_HAS_ETH1 436 #define CONFIG_HAS_ETH2 437 #define CONFIG_HAS_ETH3 438 #endif 439 440 #define CONFIG_IPADDR 192.168.1.253 441 442 #define CONFIG_HOSTNAME unknown 443 #define CONFIG_ROOTPATH "/nfsroot" 444 #define CONFIG_BOOTFILE "your.uImage" 445 446 #define CONFIG_SERVERIP 192.168.1.1 447 #define CONFIG_GATEWAYIP 192.168.1.1 448 #define CONFIG_NETMASK 255.255.255.0 449 450 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 451 452 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 453 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 454 455 #define CONFIG_BAUDRATE 115200 456 457 #define CONFIG_EXTRA_ENV_SETTINGS \ 458 "netdev=eth0\0" \ 459 "consoledev=ttyCPM\0" \ 460 "ramdiskaddr=1000000\0" \ 461 "ramdiskfile=your.ramdisk.u-boot\0" \ 462 "fdtaddr=400000\0" \ 463 "fdtfile=mpc8560ads.dtb\0" 464 465 #define CONFIG_NFSBOOTCOMMAND \ 466 "setenv bootargs root=/dev/nfs rw " \ 467 "nfsroot=$serverip:$rootpath " \ 468 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 469 "console=$consoledev,$baudrate $othbootargs;" \ 470 "tftp $loadaddr $bootfile;" \ 471 "tftp $fdtaddr $fdtfile;" \ 472 "bootm $loadaddr - $fdtaddr" 473 474 #define CONFIG_RAMBOOTCOMMAND \ 475 "setenv bootargs root=/dev/ram rw " \ 476 "console=$consoledev,$baudrate $othbootargs;" \ 477 "tftp $ramdiskaddr $ramdiskfile;" \ 478 "tftp $loadaddr $bootfile;" \ 479 "tftp $fdtaddr $fdtfile;" \ 480 "bootm $loadaddr $ramdiskaddr $fdtaddr" 481 482 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 483 484 #endif /* __CONFIG_H */ 485