1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 25 #define CONFIG_CPM2 1 /* has CPM2 */ 26 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 27 #define CONFIG_MPC8560 1 28 29 /* 30 * default CCARBAR is at 0xff700000 31 * assume U-Boot is less than 0.5MB 32 */ 33 #define CONFIG_SYS_TEXT_BASE 0xfff80000 34 35 #define CONFIG_PCI 36 #define CONFIG_PCI_INDIRECT_BRIDGE 37 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 38 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 39 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 40 #define CONFIG_ENV_OVERWRITE 41 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 42 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 43 44 /* 45 * sysclk for MPC85xx 46 * 47 * Two valid values are: 48 * 33000000 49 * 66000000 50 * 51 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 52 * is likely the desired value here, so that is now the default. 53 * The board, however, can run at 66MHz. In any event, this value 54 * must match the settings of some switches. Details can be found 55 * in the README.mpc85xxads. 56 */ 57 58 #ifndef CONFIG_SYS_CLK_FREQ 59 #define CONFIG_SYS_CLK_FREQ 33000000 60 #endif 61 62 63 /* 64 * These can be toggled for performance analysis, otherwise use default. 65 */ 66 #define CONFIG_L2_CACHE /* toggle L2 cache */ 67 #define CONFIG_BTB /* toggle branch predition */ 68 69 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 #define CONFIG_SYS_CCSRBAR 0xe0000000 75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 76 77 /* DDR Setup */ 78 #define CONFIG_FSL_DDR1 79 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 80 #define CONFIG_DDR_SPD 81 #undef CONFIG_FSL_DDR_INTERACTIVE 82 83 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 84 85 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 86 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 87 88 #define CONFIG_NUM_DDR_CONTROLLERS 1 89 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 90 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 91 92 /* I2C addresses of SPD EEPROMs */ 93 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 94 95 /* These are used when DDR doesn't use SPD. */ 96 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 97 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 98 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 99 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 100 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 101 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 102 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 103 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 104 105 /* 106 * SDRAM on the Local Bus 107 */ 108 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 109 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 110 111 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 112 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 113 114 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 115 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 116 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 117 #undef CONFIG_SYS_FLASH_CHECKSUM 118 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 119 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 120 121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 122 123 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 124 #define CONFIG_SYS_RAMBOOT 125 #else 126 #undef CONFIG_SYS_RAMBOOT 127 #endif 128 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_EMPTY_INFO 132 133 #undef CONFIG_CLOCKS_IN_MHZ 134 135 136 /* 137 * Local Bus Definitions 138 */ 139 140 /* 141 * Base Register 2 and Option Register 2 configure SDRAM. 142 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 143 * 144 * For BR2, need: 145 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 146 * port-size = 32-bits = BR2[19:20] = 11 147 * no parity checking = BR2[21:22] = 00 148 * SDRAM for MSEL = BR2[24:26] = 011 149 * Valid = BR[31] = 1 150 * 151 * 0 4 8 12 16 20 24 28 152 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 153 * 154 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 155 * FIXME: the top 17 bits of BR2. 156 */ 157 158 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 159 160 /* 161 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 162 * 163 * For OR2, need: 164 * 64MB mask for AM, OR2[0:7] = 1111 1100 165 * XAM, OR2[17:18] = 11 166 * 9 columns OR2[19-21] = 010 167 * 13 rows OR2[23-25] = 100 168 * EAD set for extra time OR[31] = 1 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 172 */ 173 174 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 175 176 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 177 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 178 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 179 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 180 181 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 182 | LSDMR_RFCR5 \ 183 | LSDMR_PRETOACT3 \ 184 | LSDMR_ACTTORW3 \ 185 | LSDMR_BL8 \ 186 | LSDMR_WRC2 \ 187 | LSDMR_CL3 \ 188 | LSDMR_RFEN \ 189 ) 190 191 /* 192 * SDRAM Controller configuration sequence. 193 */ 194 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 195 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 196 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 197 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 198 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 199 200 201 /* 202 * 32KB, 8-bit wide for ADS config reg 203 */ 204 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 205 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 206 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 207 208 #define CONFIG_SYS_INIT_RAM_LOCK 1 209 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 210 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 211 212 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 213 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 214 215 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 216 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 217 218 /* Serial Port */ 219 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 220 #undef CONFIG_CONS_NONE /* define if console on something else */ 221 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 222 223 #define CONFIG_BAUDRATE 115200 224 225 #define CONFIG_SYS_BAUDRATE_TABLE \ 226 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 227 228 /* Use the HUSH parser */ 229 #define CONFIG_SYS_HUSH_PARSER 230 #ifdef CONFIG_SYS_HUSH_PARSER 231 #endif 232 233 /* pass open firmware flat tree */ 234 #define CONFIG_OF_LIBFDT 1 235 #define CONFIG_OF_BOARD_SETUP 1 236 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 237 238 /* 239 * I2C 240 */ 241 #define CONFIG_SYS_I2C 242 #define CONFIG_SYS_I2C_FSL 243 #define CONFIG_SYS_FSL_I2C_SPEED 400000 244 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 245 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 246 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 247 248 /* RapidIO MMU */ 249 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 250 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 251 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 252 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 253 254 /* 255 * General PCI 256 * Memory space is mapped 1-1, but I/O space must start from 0. 257 */ 258 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 259 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 261 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 262 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 263 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 264 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 265 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 266 267 #if defined(CONFIG_PCI) 268 269 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 270 271 #undef CONFIG_EEPRO100 272 #undef CONFIG_TULIP 273 274 #if !defined(CONFIG_PCI_PNP) 275 #define PCI_ENET0_IOADDR 0xe0000000 276 #define PCI_ENET0_MEMADDR 0xe0000000 277 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 278 #endif 279 280 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 281 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 282 283 #endif /* CONFIG_PCI */ 284 285 286 #ifdef CONFIG_TSEC_ENET 287 288 #ifndef CONFIG_MII 289 #define CONFIG_MII 1 /* MII PHY management */ 290 #endif 291 #define CONFIG_TSEC1 1 292 #define CONFIG_TSEC1_NAME "TSEC0" 293 #define CONFIG_TSEC2 1 294 #define CONFIG_TSEC2_NAME "TSEC1" 295 #define TSEC1_PHY_ADDR 0 296 #define TSEC2_PHY_ADDR 1 297 #define TSEC1_PHYIDX 0 298 #define TSEC2_PHYIDX 0 299 #define TSEC1_FLAGS TSEC_GIGABIT 300 #define TSEC2_FLAGS TSEC_GIGABIT 301 302 /* Options are: TSEC[0-1] */ 303 #define CONFIG_ETHPRIME "TSEC0" 304 305 #endif /* CONFIG_TSEC_ENET */ 306 307 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 308 309 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 310 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 311 312 #if (CONFIG_ETHER_INDEX == 2) 313 /* 314 * - Rx-CLK is CLK13 315 * - Tx-CLK is CLK14 316 * - Select bus for bd/buffers 317 * - Full duplex 318 */ 319 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 320 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 321 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 322 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 323 #define FETH2_RST 0x01 324 #elif (CONFIG_ETHER_INDEX == 3) 325 /* need more definitions here for FE3 */ 326 #define FETH3_RST 0x80 327 #endif /* CONFIG_ETHER_INDEX */ 328 329 #ifndef CONFIG_MII 330 #define CONFIG_MII 1 /* MII PHY management */ 331 #endif 332 333 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 334 335 /* 336 * GPIO pins used for bit-banged MII communications 337 */ 338 #define MDIO_PORT 2 /* Port C */ 339 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 340 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 341 #define MDC_DECLARE MDIO_DECLARE 342 343 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 344 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 345 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 346 347 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 348 else iop->pdat &= ~0x00400000 349 350 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 351 else iop->pdat &= ~0x00200000 352 353 #define MIIDELAY udelay(1) 354 355 #endif 356 357 358 /* 359 * Environment 360 */ 361 #ifndef CONFIG_SYS_RAMBOOT 362 #define CONFIG_ENV_IS_IN_FLASH 1 363 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 364 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 365 #define CONFIG_ENV_SIZE 0x2000 366 #else 367 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 368 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 369 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 370 #define CONFIG_ENV_SIZE 0x2000 371 #endif 372 373 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 374 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 375 376 /* 377 * BOOTP options 378 */ 379 #define CONFIG_BOOTP_BOOTFILESIZE 380 #define CONFIG_BOOTP_BOOTPATH 381 #define CONFIG_BOOTP_GATEWAY 382 #define CONFIG_BOOTP_HOSTNAME 383 384 385 /* 386 * Command line configuration. 387 */ 388 #include <config_cmd_default.h> 389 390 #define CONFIG_CMD_PING 391 #define CONFIG_CMD_I2C 392 #define CONFIG_CMD_ELF 393 #define CONFIG_CMD_IRQ 394 #define CONFIG_CMD_SETEXPR 395 #define CONFIG_CMD_REGINFO 396 397 #if defined(CONFIG_PCI) 398 #define CONFIG_CMD_PCI 399 #endif 400 401 #if defined(CONFIG_ETHER_ON_FCC) 402 #define CONFIG_CMD_MII 403 #endif 404 405 #if defined(CONFIG_SYS_RAMBOOT) 406 #undef CONFIG_CMD_SAVEENV 407 #undef CONFIG_CMD_LOADS 408 #endif 409 410 411 #undef CONFIG_WATCHDOG /* watchdog disabled */ 412 413 /* 414 * Miscellaneous configurable options 415 */ 416 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 417 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 418 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 419 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 420 421 #if defined(CONFIG_CMD_KGDB) 422 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 423 #else 424 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 425 #endif 426 427 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 428 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 429 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 430 431 /* 432 * For booting Linux, the board info and command line data 433 * have to be in the first 64 MB of memory, since this is 434 * the maximum mapped by the Linux kernel during initialization. 435 */ 436 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 437 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 438 439 #if defined(CONFIG_CMD_KGDB) 440 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 441 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 442 #endif 443 444 445 /* 446 * Environment Configuration 447 */ 448 449 /* The mac addresses for all ethernet interface */ 450 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 451 #define CONFIG_HAS_ETH0 452 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 453 #define CONFIG_HAS_ETH1 454 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 455 #define CONFIG_HAS_ETH2 456 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 457 #define CONFIG_HAS_ETH3 458 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 459 #endif 460 461 #define CONFIG_IPADDR 192.168.1.253 462 463 #define CONFIG_HOSTNAME unknown 464 #define CONFIG_ROOTPATH "/nfsroot" 465 #define CONFIG_BOOTFILE "your.uImage" 466 467 #define CONFIG_SERVERIP 192.168.1.1 468 #define CONFIG_GATEWAYIP 192.168.1.1 469 #define CONFIG_NETMASK 255.255.255.0 470 471 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 472 473 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 474 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 475 476 #define CONFIG_BAUDRATE 115200 477 478 #define CONFIG_EXTRA_ENV_SETTINGS \ 479 "netdev=eth0\0" \ 480 "consoledev=ttyCPM\0" \ 481 "ramdiskaddr=1000000\0" \ 482 "ramdiskfile=your.ramdisk.u-boot\0" \ 483 "fdtaddr=400000\0" \ 484 "fdtfile=mpc8560ads.dtb\0" 485 486 #define CONFIG_NFSBOOTCOMMAND \ 487 "setenv bootargs root=/dev/nfs rw " \ 488 "nfsroot=$serverip:$rootpath " \ 489 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 490 "console=$consoledev,$baudrate $othbootargs;" \ 491 "tftp $loadaddr $bootfile;" \ 492 "tftp $fdtaddr $fdtfile;" \ 493 "bootm $loadaddr - $fdtaddr" 494 495 #define CONFIG_RAMBOOTCOMMAND \ 496 "setenv bootargs root=/dev/ram rw " \ 497 "console=$consoledev,$baudrate $othbootargs;" \ 498 "tftp $ramdiskaddr $ramdiskfile;" \ 499 "tftp $loadaddr $bootfile;" \ 500 "tftp $fdtaddr $fdtfile;" \ 501 "bootm $loadaddr $ramdiskaddr $fdtaddr" 502 503 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 504 505 #endif /* __CONFIG_H */ 506