1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8560ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8560 1 /* MPC8560 specific */ 42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 43 44 #define CONFIG_PCI 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 49 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 50 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 53 54 /* 55 * sysclk for MPC85xx 56 * 57 * Two valid values are: 58 * 33000000 59 * 66000000 60 * 61 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 62 * is likely the desired value here, so that is now the default. 63 * The board, however, can run at 66MHz. In any event, this value 64 * must match the settings of some switches. Details can be found 65 * in the README.mpc85xxads. 66 */ 67 68 #ifndef CONFIG_SYS_CLK_FREQ 69 #define CONFIG_SYS_CLK_FREQ 33000000 70 #endif 71 72 73 /* 74 * These can be toggled for performance analysis, otherwise use default. 75 */ 76 #define CONFIG_L2_CACHE /* toggle L2 cache */ 77 #define CONFIG_BTB /* toggle branch predition */ 78 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 79 80 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 81 82 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 83 84 #undef CFG_DRAM_TEST /* memory test, takes time */ 85 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 86 #define CFG_MEMTEST_END 0x00400000 87 88 89 /* 90 * Base addresses -- Note these are effective addresses where the 91 * actual resources get mapped (not physical addresses) 92 */ 93 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 94 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 95 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 96 97 98 /* 99 * DDR Setup 100 */ 101 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 102 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 103 104 #if defined(CONFIG_SPD_EEPROM) 105 /* 106 * Determine DDR configuration from I2C interface. 107 */ 108 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 109 110 #else 111 /* 112 * Manually set up DDR parameters 113 */ 114 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 115 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 116 #define CFG_DDR_CS0_CONFIG 0x80000002 117 #define CFG_DDR_TIMING_1 0x37344321 118 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 119 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 120 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 121 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 122 #endif 123 124 125 /* 126 * SDRAM on the Local Bus 127 */ 128 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 129 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 130 131 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 132 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 133 134 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 135 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 136 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 137 #undef CFG_FLASH_CHECKSUM 138 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 139 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 140 141 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 142 143 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 144 #define CFG_RAMBOOT 145 #else 146 #undef CFG_RAMBOOT 147 #endif 148 149 #define CFG_FLASH_CFI_DRIVER 150 #define CFG_FLASH_CFI 151 #define CFG_FLASH_EMPTY_INFO 152 153 #undef CONFIG_CLOCKS_IN_MHZ 154 155 156 /* 157 * Local Bus Definitions 158 */ 159 160 /* 161 * Base Register 2 and Option Register 2 configure SDRAM. 162 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 163 * 164 * For BR2, need: 165 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 166 * port-size = 32-bits = BR2[19:20] = 11 167 * no parity checking = BR2[21:22] = 00 168 * SDRAM for MSEL = BR2[24:26] = 011 169 * Valid = BR[31] = 1 170 * 171 * 0 4 8 12 16 20 24 28 172 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 173 * 174 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 175 * FIXME: the top 17 bits of BR2. 176 */ 177 178 #define CFG_BR2_PRELIM 0xf0001861 179 180 /* 181 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 182 * 183 * For OR2, need: 184 * 64MB mask for AM, OR2[0:7] = 1111 1100 185 * XAM, OR2[17:18] = 11 186 * 9 columns OR2[19-21] = 010 187 * 13 rows OR2[23-25] = 100 188 * EAD set for extra time OR[31] = 1 189 * 190 * 0 4 8 12 16 20 24 28 191 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 192 */ 193 194 #define CFG_OR2_PRELIM 0xfc006901 195 196 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 197 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 198 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 199 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 200 201 /* 202 * LSDMR masks 203 */ 204 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 205 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 206 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 207 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 208 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 209 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 210 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 211 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 212 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 213 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 214 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 215 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 216 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 217 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 218 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 219 220 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 221 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 222 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 223 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 228 229 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 230 | CFG_LBC_LSDMR_RFCR5 \ 231 | CFG_LBC_LSDMR_PRETOACT3 \ 232 | CFG_LBC_LSDMR_ACTTORW3 \ 233 | CFG_LBC_LSDMR_BL8 \ 234 | CFG_LBC_LSDMR_WRC2 \ 235 | CFG_LBC_LSDMR_CL3 \ 236 | CFG_LBC_LSDMR_RFEN \ 237 ) 238 239 /* 240 * SDRAM Controller configuration sequence. 241 */ 242 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 243 | CFG_LBC_LSDMR_OP_PCHALL) 244 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 245 | CFG_LBC_LSDMR_OP_ARFRSH) 246 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 247 | CFG_LBC_LSDMR_OP_ARFRSH) 248 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 249 | CFG_LBC_LSDMR_OP_MRW) 250 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 251 | CFG_LBC_LSDMR_OP_NORMAL) 252 253 254 /* 255 * 32KB, 8-bit wide for ADS config reg 256 */ 257 #define CFG_BR4_PRELIM 0xf8000801 258 #define CFG_OR4_PRELIM 0xffffe1f1 259 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 260 261 #define CONFIG_L1_INIT_RAM 262 #define CFG_INIT_RAM_LOCK 1 263 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 264 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 265 266 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 267 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 268 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 269 270 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 271 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 272 273 /* Serial Port */ 274 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 275 #undef CONFIG_CONS_NONE /* define if console on something else */ 276 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 277 278 #define CONFIG_BAUDRATE 115200 279 280 #define CFG_BAUDRATE_TABLE \ 281 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 282 283 /* Use the HUSH parser */ 284 #define CFG_HUSH_PARSER 285 #ifdef CFG_HUSH_PARSER 286 #define CFG_PROMPT_HUSH_PS2 "> " 287 #endif 288 289 /* I2C */ 290 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 291 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 292 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 293 #define CFG_I2C_SLAVE 0x7F 294 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 295 296 /* RapidIO MMU */ 297 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 298 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 299 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 300 301 /* 302 * General PCI 303 * Addresses are mapped 1-1. 304 */ 305 #define CFG_PCI1_MEM_BASE 0x80000000 306 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 307 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 308 #define CFG_PCI1_IO_BASE 0xe2000000 309 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 310 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 311 312 #if defined(CONFIG_PCI) 313 314 #define CONFIG_NET_MULTI 315 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 316 317 #undef CONFIG_EEPRO100 318 #undef CONFIG_TULIP 319 320 #if !defined(CONFIG_PCI_PNP) 321 #define PCI_ENET0_IOADDR 0xe0000000 322 #define PCI_ENET0_MEMADDR 0xe0000000 323 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 324 #endif 325 326 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 327 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 328 329 #endif /* CONFIG_PCI */ 330 331 332 #if defined(CONFIG_TSEC_ENET) 333 334 #ifndef CONFIG_NET_MULTI 335 #define CONFIG_NET_MULTI 1 336 #endif 337 338 #define CONFIG_MII 1 /* MII PHY management */ 339 #define CONFIG_MPC85XX_TSEC1 1 340 #define CONFIG_MPC85XX_TSEC2 1 341 #undef CONFIG_MPC85XX_FEC 342 #define TSEC1_PHY_ADDR 0 343 #define TSEC2_PHY_ADDR 1 344 #define TSEC1_PHYIDX 0 345 #define TSEC2_PHYIDX 0 346 #define CONFIG_ETHPRIME "MOTO ENET0" 347 348 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ 349 350 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 351 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 352 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 353 354 #if (CONFIG_ETHER_INDEX == 2) 355 /* 356 * - Rx-CLK is CLK13 357 * - Tx-CLK is CLK14 358 * - Select bus for bd/buffers 359 * - Full duplex 360 */ 361 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 362 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 363 #define CFG_CPMFCR_RAMTYPE 0 364 #define CFG_FCC_PSMR (FCC_PSMR_FDE) 365 #define FETH2_RST 0x01 366 #elif (CONFIG_ETHER_INDEX == 3) 367 /* need more definitions here for FE3 */ 368 #define FETH3_RST 0x80 369 #endif /* CONFIG_ETHER_INDEX */ 370 371 #define CONFIG_MII /* MII PHY management */ 372 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 373 374 /* 375 * GPIO pins used for bit-banged MII communications 376 */ 377 #define MDIO_PORT 2 /* Port C */ 378 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 379 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 380 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 381 382 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 383 else iop->pdat &= ~0x00400000 384 385 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 386 else iop->pdat &= ~0x00200000 387 388 #define MIIDELAY udelay(1) 389 390 #endif 391 392 393 /* 394 * Environment 395 */ 396 #ifndef CFG_RAMBOOT 397 #define CFG_ENV_IS_IN_FLASH 1 398 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 399 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 400 #define CFG_ENV_SIZE 0x2000 401 #else 402 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 403 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 404 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 405 #define CFG_ENV_SIZE 0x2000 406 #endif 407 408 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 409 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 410 411 #if defined(CFG_RAMBOOT) 412 #if defined(CONFIG_PCI) 413 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 414 | CFG_CMD_PING \ 415 | CFG_CMD_PCI \ 416 | CFG_CMD_I2C) \ 417 & \ 418 ~(CFG_CMD_ENV \ 419 | CFG_CMD_LOADS)) 420 #elif defined(CONFIG_TSEC_ENET) 421 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 422 | CFG_CMD_PING \ 423 | CFG_CMD_I2C) \ 424 & ~(CFG_CMD_ENV)) 425 #elif defined(CONFIG_ETHER_ON_FCC) 426 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 427 | CFG_CMD_MII \ 428 | CFG_CMD_PING \ 429 | CFG_CMD_I2C) \ 430 & ~(CFG_CMD_ENV)) 431 #endif 432 #else 433 #if defined(CONFIG_PCI) 434 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 435 | CFG_CMD_PCI \ 436 | CFG_CMD_PING \ 437 | CFG_CMD_I2C) 438 #elif defined(CONFIG_TSEC_ENET) 439 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 440 | CFG_CMD_PING \ 441 | CFG_CMD_I2C) 442 #elif defined(CONFIG_ETHER_ON_FCC) 443 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 444 | CFG_CMD_MII \ 445 | CFG_CMD_PING \ 446 | CFG_CMD_I2C) 447 #endif 448 #endif 449 450 #include <cmd_confdefs.h> 451 452 #undef CONFIG_WATCHDOG /* watchdog disabled */ 453 454 /* 455 * Miscellaneous configurable options 456 */ 457 #define CFG_LONGHELP /* undef to save memory */ 458 #define CFG_LOAD_ADDR 0x1000000 /* default load address */ 459 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 460 461 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 462 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 463 #else 464 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 465 #endif 466 467 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 468 #define CFG_MAXARGS 16 /* max number of command args */ 469 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 470 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 471 472 /* 473 * For booting Linux, the board info and command line data 474 * have to be in the first 8 MB of memory, since this is 475 * the maximum mapped by the Linux kernel during initialization. 476 */ 477 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 478 479 /* Cache Configuration */ 480 #define CFG_DCACHE_SIZE 32768 481 #define CFG_CACHELINE_SIZE 32 482 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 483 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 484 #endif 485 486 /* 487 * Internal Definitions 488 * 489 * Boot Flags 490 */ 491 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 492 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 493 494 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 495 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 496 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 497 #endif 498 499 500 /* 501 * Environment Configuration 502 */ 503 504 /* The mac addresses for all ethernet interface */ 505 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 506 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 507 #define CONFIG_HAS_ETH1 508 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 509 #define CONFIG_HAS_ETH2 510 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 511 #endif 512 513 #define CONFIG_IPADDR 192.168.1.253 514 515 #define CONFIG_HOSTNAME unknown 516 #define CONFIG_ROOTPATH /nfsroot 517 #define CONFIG_BOOTFILE your.uImage 518 519 #define CONFIG_SERVERIP 192.168.1.1 520 #define CONFIG_GATEWAYIP 192.168.1.1 521 #define CONFIG_NETMASK 255.255.255.0 522 523 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 524 525 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 526 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 527 528 #define CONFIG_BAUDRATE 115200 529 530 #define CONFIG_EXTRA_ENV_SETTINGS \ 531 "netdev=eth0\0" \ 532 "consoledev=ttyS0\0" \ 533 "ramdiskaddr=400000\0" \ 534 "ramdiskfile=your.ramdisk.u-boot\0" 535 536 #define CONFIG_NFSBOOTCOMMAND \ 537 "setenv bootargs root=/dev/nfs rw " \ 538 "nfsroot=$serverip:$rootpath " \ 539 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 540 "console=$consoledev,$baudrate $othbootargs;" \ 541 "tftp $loadaddr $bootfile;" \ 542 "bootm $loadaddr" 543 544 #define CONFIG_RAMBOOTCOMMAND \ 545 "setenv bootargs root=/dev/ram rw " \ 546 "console=$consoledev,$baudrate $othbootargs;" \ 547 "tftp $ramdiskaddr $ramdiskfile;" \ 548 "tftp $loadaddr $bootfile;" \ 549 "bootm $loadaddr $ramdiskaddr" 550 551 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 552 553 #endif /* __CONFIG_H */ 554