1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8560ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_CPM2 1 /* has CPM2 */ 42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 43 44 #define CONFIG_PCI 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 49 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 50 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 51 52 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 54 55 56 /* 57 * sysclk for MPC85xx 58 * 59 * Two valid values are: 60 * 33000000 61 * 66000000 62 * 63 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 64 * is likely the desired value here, so that is now the default. 65 * The board, however, can run at 66MHz. In any event, this value 66 * must match the settings of some switches. Details can be found 67 * in the README.mpc85xxads. 68 */ 69 70 #ifndef CONFIG_SYS_CLK_FREQ 71 #define CONFIG_SYS_CLK_FREQ 33000000 72 #endif 73 74 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_L2_CACHE /* toggle L2 cache */ 79 #define CONFIG_BTB /* toggle branch predition */ 80 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 81 82 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 83 84 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 85 86 #undef CFG_DRAM_TEST /* memory test, takes time */ 87 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 88 #define CFG_MEMTEST_END 0x00400000 89 90 91 /* 92 * Base addresses -- Note these are effective addresses where the 93 * actual resources get mapped (not physical addresses) 94 */ 95 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 96 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 97 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 98 99 100 /* 101 * DDR Setup 102 */ 103 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 104 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 105 106 #if defined(CONFIG_SPD_EEPROM) 107 /* 108 * Determine DDR configuration from I2C interface. 109 */ 110 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 111 112 #else 113 /* 114 * Manually set up DDR parameters 115 */ 116 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 117 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 118 #define CFG_DDR_CS0_CONFIG 0x80000002 119 #define CFG_DDR_TIMING_1 0x37344321 120 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 121 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 122 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 123 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 124 #endif 125 126 127 /* 128 * SDRAM on the Local Bus 129 */ 130 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 131 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 132 133 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 134 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 135 136 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 137 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 138 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 139 #undef CFG_FLASH_CHECKSUM 140 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 141 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 142 143 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 144 145 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 146 #define CFG_RAMBOOT 147 #else 148 #undef CFG_RAMBOOT 149 #endif 150 151 #define CFG_FLASH_CFI_DRIVER 152 #define CFG_FLASH_CFI 153 #define CFG_FLASH_EMPTY_INFO 154 155 #undef CONFIG_CLOCKS_IN_MHZ 156 157 158 /* 159 * Local Bus Definitions 160 */ 161 162 /* 163 * Base Register 2 and Option Register 2 configure SDRAM. 164 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 165 * 166 * For BR2, need: 167 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 168 * port-size = 32-bits = BR2[19:20] = 11 169 * no parity checking = BR2[21:22] = 00 170 * SDRAM for MSEL = BR2[24:26] = 011 171 * Valid = BR[31] = 1 172 * 173 * 0 4 8 12 16 20 24 28 174 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 175 * 176 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 177 * FIXME: the top 17 bits of BR2. 178 */ 179 180 #define CFG_BR2_PRELIM 0xf0001861 181 182 /* 183 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 184 * 185 * For OR2, need: 186 * 64MB mask for AM, OR2[0:7] = 1111 1100 187 * XAM, OR2[17:18] = 11 188 * 9 columns OR2[19-21] = 010 189 * 13 rows OR2[23-25] = 100 190 * EAD set for extra time OR[31] = 1 191 * 192 * 0 4 8 12 16 20 24 28 193 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 194 */ 195 196 #define CFG_OR2_PRELIM 0xfc006901 197 198 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 199 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 200 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 201 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 202 203 /* 204 * LSDMR masks 205 */ 206 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 207 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 208 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 209 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 210 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 211 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 212 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 213 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 214 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 215 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 216 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 217 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 218 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 219 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 220 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 221 222 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 223 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 224 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 230 231 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 232 | CFG_LBC_LSDMR_RFCR5 \ 233 | CFG_LBC_LSDMR_PRETOACT3 \ 234 | CFG_LBC_LSDMR_ACTTORW3 \ 235 | CFG_LBC_LSDMR_BL8 \ 236 | CFG_LBC_LSDMR_WRC2 \ 237 | CFG_LBC_LSDMR_CL3 \ 238 | CFG_LBC_LSDMR_RFEN \ 239 ) 240 241 /* 242 * SDRAM Controller configuration sequence. 243 */ 244 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 245 | CFG_LBC_LSDMR_OP_PCHALL) 246 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 247 | CFG_LBC_LSDMR_OP_ARFRSH) 248 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 249 | CFG_LBC_LSDMR_OP_ARFRSH) 250 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 251 | CFG_LBC_LSDMR_OP_MRW) 252 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 253 | CFG_LBC_LSDMR_OP_NORMAL) 254 255 256 /* 257 * 32KB, 8-bit wide for ADS config reg 258 */ 259 #define CFG_BR4_PRELIM 0xf8000801 260 #define CFG_OR4_PRELIM 0xffffe1f1 261 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 262 263 #define CONFIG_L1_INIT_RAM 264 #define CFG_INIT_RAM_LOCK 1 265 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 266 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 267 268 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 269 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 270 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 271 272 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 273 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 274 275 /* Serial Port */ 276 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 277 #undef CONFIG_CONS_NONE /* define if console on something else */ 278 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 279 280 #define CONFIG_BAUDRATE 115200 281 282 #define CFG_BAUDRATE_TABLE \ 283 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 284 285 /* Use the HUSH parser */ 286 #define CFG_HUSH_PARSER 287 #ifdef CFG_HUSH_PARSER 288 #define CFG_PROMPT_HUSH_PS2 "> " 289 #endif 290 291 /* I2C */ 292 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 293 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 294 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 295 #define CFG_I2C_SLAVE 0x7F 296 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 297 298 /* RapidIO MMU */ 299 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 300 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 301 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 302 303 /* 304 * General PCI 305 * Addresses are mapped 1-1. 306 */ 307 #define CFG_PCI1_MEM_BASE 0x80000000 308 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 309 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 310 #define CFG_PCI1_IO_BASE 0xe2000000 311 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 312 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 313 314 #if defined(CONFIG_PCI) 315 316 #define CONFIG_NET_MULTI 317 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 318 319 #undef CONFIG_EEPRO100 320 #undef CONFIG_TULIP 321 322 #if !defined(CONFIG_PCI_PNP) 323 #define PCI_ENET0_IOADDR 0xe0000000 324 #define PCI_ENET0_MEMADDR 0xe0000000 325 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 326 #endif 327 328 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 329 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 330 331 #endif /* CONFIG_PCI */ 332 333 334 #if defined(CONFIG_TSEC_ENET) 335 336 #ifndef CONFIG_NET_MULTI 337 #define CONFIG_NET_MULTI 1 338 #endif 339 340 #define CONFIG_MII 1 /* MII PHY management */ 341 #define CONFIG_MPC85XX_TSEC1 1 342 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" 343 #define CONFIG_MPC85XX_TSEC2 1 344 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" 345 #undef CONFIG_MPC85XX_FEC 346 #define TSEC1_PHY_ADDR 0 347 #define TSEC2_PHY_ADDR 1 348 #define TSEC1_PHYIDX 0 349 #define TSEC2_PHYIDX 0 350 351 /* Options are: TSEC[0-1] */ 352 #define CONFIG_ETHPRIME "TSEC0" 353 354 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ 355 356 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 357 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 358 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 359 360 #if (CONFIG_ETHER_INDEX == 2) 361 /* 362 * - Rx-CLK is CLK13 363 * - Tx-CLK is CLK14 364 * - Select bus for bd/buffers 365 * - Full duplex 366 */ 367 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 368 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 369 #define CFG_CPMFCR_RAMTYPE 0 370 #define CFG_FCC_PSMR (FCC_PSMR_FDE) 371 #define FETH2_RST 0x01 372 #elif (CONFIG_ETHER_INDEX == 3) 373 /* need more definitions here for FE3 */ 374 #define FETH3_RST 0x80 375 #endif /* CONFIG_ETHER_INDEX */ 376 377 #define CONFIG_MII /* MII PHY management */ 378 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 379 380 /* 381 * GPIO pins used for bit-banged MII communications 382 */ 383 #define MDIO_PORT 2 /* Port C */ 384 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 385 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 386 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 387 388 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 389 else iop->pdat &= ~0x00400000 390 391 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 392 else iop->pdat &= ~0x00200000 393 394 #define MIIDELAY udelay(1) 395 396 #endif 397 398 399 /* 400 * Environment 401 */ 402 #ifndef CFG_RAMBOOT 403 #define CFG_ENV_IS_IN_FLASH 1 404 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 405 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 406 #define CFG_ENV_SIZE 0x2000 407 #else 408 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 409 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 410 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 411 #define CFG_ENV_SIZE 0x2000 412 #endif 413 414 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 415 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 416 417 #if defined(CFG_RAMBOOT) 418 #if defined(CONFIG_PCI) 419 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 420 | CFG_CMD_PING \ 421 | CFG_CMD_PCI \ 422 | CFG_CMD_I2C) \ 423 & \ 424 ~(CFG_CMD_ENV \ 425 | CFG_CMD_LOADS)) 426 #elif defined(CONFIG_TSEC_ENET) 427 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 428 | CFG_CMD_PING \ 429 | CFG_CMD_I2C) \ 430 & ~(CFG_CMD_ENV)) 431 #elif defined(CONFIG_ETHER_ON_FCC) 432 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 433 | CFG_CMD_MII \ 434 | CFG_CMD_PING \ 435 | CFG_CMD_I2C) \ 436 & ~(CFG_CMD_ENV)) 437 #endif 438 #else 439 #if defined(CONFIG_PCI) 440 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 441 | CFG_CMD_PCI \ 442 | CFG_CMD_PING \ 443 | CFG_CMD_I2C) 444 #elif defined(CONFIG_TSEC_ENET) 445 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 446 | CFG_CMD_PING \ 447 | CFG_CMD_I2C) 448 #elif defined(CONFIG_ETHER_ON_FCC) 449 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 450 | CFG_CMD_MII \ 451 | CFG_CMD_PING \ 452 | CFG_CMD_I2C) 453 #endif 454 #endif 455 456 #include <cmd_confdefs.h> 457 458 #undef CONFIG_WATCHDOG /* watchdog disabled */ 459 460 /* 461 * Miscellaneous configurable options 462 */ 463 #define CFG_LONGHELP /* undef to save memory */ 464 #define CFG_LOAD_ADDR 0x1000000 /* default load address */ 465 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 466 467 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 468 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 469 #else 470 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 471 #endif 472 473 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 474 #define CFG_MAXARGS 16 /* max number of command args */ 475 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 476 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 477 478 /* 479 * For booting Linux, the board info and command line data 480 * have to be in the first 8 MB of memory, since this is 481 * the maximum mapped by the Linux kernel during initialization. 482 */ 483 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 484 485 /* Cache Configuration */ 486 #define CFG_DCACHE_SIZE 32768 487 #define CFG_CACHELINE_SIZE 32 488 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 489 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 490 #endif 491 492 /* 493 * Internal Definitions 494 * 495 * Boot Flags 496 */ 497 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 498 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 499 500 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 501 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 502 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 503 #endif 504 505 506 /* 507 * Environment Configuration 508 */ 509 510 /* The mac addresses for all ethernet interface */ 511 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 512 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 513 #define CONFIG_HAS_ETH1 514 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 515 #define CONFIG_HAS_ETH2 516 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 517 #endif 518 519 #define CONFIG_IPADDR 192.168.1.253 520 521 #define CONFIG_HOSTNAME unknown 522 #define CONFIG_ROOTPATH /nfsroot 523 #define CONFIG_BOOTFILE your.uImage 524 525 #define CONFIG_SERVERIP 192.168.1.1 526 #define CONFIG_GATEWAYIP 192.168.1.1 527 #define CONFIG_NETMASK 255.255.255.0 528 529 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 530 531 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 532 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 533 534 #define CONFIG_BAUDRATE 115200 535 536 #define CONFIG_EXTRA_ENV_SETTINGS \ 537 "netdev=eth0\0" \ 538 "consoledev=ttyS0\0" \ 539 "ramdiskaddr=400000\0" \ 540 "ramdiskfile=your.ramdisk.u-boot\0" 541 542 #define CONFIG_NFSBOOTCOMMAND \ 543 "setenv bootargs root=/dev/nfs rw " \ 544 "nfsroot=$serverip:$rootpath " \ 545 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 546 "console=$consoledev,$baudrate $othbootargs;" \ 547 "tftp $loadaddr $bootfile;" \ 548 "bootm $loadaddr" 549 550 #define CONFIG_RAMBOOTCOMMAND \ 551 "setenv bootargs root=/dev/ram rw " \ 552 "console=$consoledev,$baudrate $othbootargs;" \ 553 "tftp $ramdiskaddr $ramdiskfile;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "bootm $loadaddr $ramdiskaddr" 556 557 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 558 559 #endif /* __CONFIG_H */ 560