1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_CPM2 1 /* has CPM2 */ 23 24 /* 25 * default CCARBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 29 #define CONFIG_PCI_INDIRECT_BRIDGE 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 32 #define CONFIG_ENV_OVERWRITE 33 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 34 35 /* 36 * sysclk for MPC85xx 37 * 38 * Two valid values are: 39 * 33000000 40 * 66000000 41 * 42 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 43 * is likely the desired value here, so that is now the default. 44 * The board, however, can run at 66MHz. In any event, this value 45 * must match the settings of some switches. Details can be found 46 * in the README.mpc85xxads. 47 */ 48 49 #ifndef CONFIG_SYS_CLK_FREQ 50 #define CONFIG_SYS_CLK_FREQ 33000000 51 #endif 52 53 /* 54 * These can be toggled for performance analysis, otherwise use default. 55 */ 56 #define CONFIG_L2_CACHE /* toggle L2 cache */ 57 #define CONFIG_BTB /* toggle branch predition */ 58 59 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 60 61 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 62 #define CONFIG_SYS_MEMTEST_END 0x00400000 63 64 #define CONFIG_SYS_CCSRBAR 0xe0000000 65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 66 67 /* DDR Setup */ 68 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 69 #define CONFIG_DDR_SPD 70 #undef CONFIG_FSL_DDR_INTERACTIVE 71 72 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 73 74 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 75 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 76 77 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 78 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 79 80 /* I2C addresses of SPD EEPROMs */ 81 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 82 83 /* These are used when DDR doesn't use SPD. */ 84 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 85 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 86 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 87 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 88 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 89 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 90 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 91 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 92 93 /* 94 * SDRAM on the Local Bus 95 */ 96 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 97 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 98 99 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 100 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 101 102 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 103 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 104 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 105 #undef CONFIG_SYS_FLASH_CHECKSUM 106 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 107 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 108 109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 110 111 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 112 #define CONFIG_SYS_RAMBOOT 113 #else 114 #undef CONFIG_SYS_RAMBOOT 115 #endif 116 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_EMPTY_INFO 120 121 #undef CONFIG_CLOCKS_IN_MHZ 122 123 /* 124 * Local Bus Definitions 125 */ 126 127 /* 128 * Base Register 2 and Option Register 2 configure SDRAM. 129 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 130 * 131 * For BR2, need: 132 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 133 * port-size = 32-bits = BR2[19:20] = 11 134 * no parity checking = BR2[21:22] = 00 135 * SDRAM for MSEL = BR2[24:26] = 011 136 * Valid = BR[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 140 * 141 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 142 * FIXME: the top 17 bits of BR2. 143 */ 144 145 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 146 147 /* 148 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 149 * 150 * For OR2, need: 151 * 64MB mask for AM, OR2[0:7] = 1111 1100 152 * XAM, OR2[17:18] = 11 153 * 9 columns OR2[19-21] = 010 154 * 13 rows OR2[23-25] = 100 155 * EAD set for extra time OR[31] = 1 156 * 157 * 0 4 8 12 16 20 24 28 158 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 159 */ 160 161 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 162 163 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 164 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 165 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 166 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 167 168 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 169 | LSDMR_RFCR5 \ 170 | LSDMR_PRETOACT3 \ 171 | LSDMR_ACTTORW3 \ 172 | LSDMR_BL8 \ 173 | LSDMR_WRC2 \ 174 | LSDMR_CL3 \ 175 | LSDMR_RFEN \ 176 ) 177 178 /* 179 * SDRAM Controller configuration sequence. 180 */ 181 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 182 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 183 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 184 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 185 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 186 187 /* 188 * 32KB, 8-bit wide for ADS config reg 189 */ 190 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 191 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 192 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 193 194 #define CONFIG_SYS_INIT_RAM_LOCK 1 195 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 196 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 197 198 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 199 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 200 201 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 202 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 203 204 /* Serial Port */ 205 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 206 #undef CONFIG_CONS_NONE /* define if console on something else */ 207 208 #define CONFIG_SYS_BAUDRATE_TABLE \ 209 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 210 211 /* 212 * I2C 213 */ 214 #define CONFIG_SYS_I2C 215 #define CONFIG_SYS_I2C_FSL 216 #define CONFIG_SYS_FSL_I2C_SPEED 400000 217 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 218 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 219 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 220 221 /* RapidIO MMU */ 222 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 223 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 224 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 225 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 226 227 /* 228 * General PCI 229 * Memory space is mapped 1-1, but I/O space must start from 0. 230 */ 231 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 232 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 233 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 234 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 235 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 236 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 237 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 238 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 239 240 #if defined(CONFIG_PCI) 241 #undef CONFIG_EEPRO100 242 #undef CONFIG_TULIP 243 244 #if !defined(CONFIG_PCI_PNP) 245 #define PCI_ENET0_IOADDR 0xe0000000 246 #define PCI_ENET0_MEMADDR 0xe0000000 247 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 248 #endif 249 250 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 251 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 252 253 #endif /* CONFIG_PCI */ 254 255 #ifdef CONFIG_TSEC_ENET 256 257 #ifndef CONFIG_MII 258 #define CONFIG_MII 1 /* MII PHY management */ 259 #endif 260 #define CONFIG_TSEC1 1 261 #define CONFIG_TSEC1_NAME "TSEC0" 262 #define CONFIG_TSEC2 1 263 #define CONFIG_TSEC2_NAME "TSEC1" 264 #define TSEC1_PHY_ADDR 0 265 #define TSEC2_PHY_ADDR 1 266 #define TSEC1_PHYIDX 0 267 #define TSEC2_PHYIDX 0 268 #define TSEC1_FLAGS TSEC_GIGABIT 269 #define TSEC2_FLAGS TSEC_GIGABIT 270 271 /* Options are: TSEC[0-1] */ 272 #define CONFIG_ETHPRIME "TSEC0" 273 274 #endif /* CONFIG_TSEC_ENET */ 275 276 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 277 278 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 279 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 280 281 #if (CONFIG_ETHER_INDEX == 2) 282 /* 283 * - Rx-CLK is CLK13 284 * - Tx-CLK is CLK14 285 * - Select bus for bd/buffers 286 * - Full duplex 287 */ 288 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 289 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 290 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 291 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 292 #define FETH2_RST 0x01 293 #elif (CONFIG_ETHER_INDEX == 3) 294 /* need more definitions here for FE3 */ 295 #define FETH3_RST 0x80 296 #endif /* CONFIG_ETHER_INDEX */ 297 298 #ifndef CONFIG_MII 299 #define CONFIG_MII 1 /* MII PHY management */ 300 #endif 301 302 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 303 304 /* 305 * GPIO pins used for bit-banged MII communications 306 */ 307 #define MDIO_PORT 2 /* Port C */ 308 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 309 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 310 #define MDC_DECLARE MDIO_DECLARE 311 312 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 313 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 314 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 315 316 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 317 else iop->pdat &= ~0x00400000 318 319 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 320 else iop->pdat &= ~0x00200000 321 322 #define MIIDELAY udelay(1) 323 324 #endif 325 326 /* 327 * Environment 328 */ 329 #ifndef CONFIG_SYS_RAMBOOT 330 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 331 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 332 #define CONFIG_ENV_SIZE 0x2000 333 #else 334 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 335 #define CONFIG_ENV_SIZE 0x2000 336 #endif 337 338 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 339 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 340 341 /* 342 * BOOTP options 343 */ 344 #define CONFIG_BOOTP_BOOTFILESIZE 345 346 #undef CONFIG_WATCHDOG /* watchdog disabled */ 347 348 /* 349 * Miscellaneous configurable options 350 */ 351 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 352 353 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 354 355 /* 356 * For booting Linux, the board info and command line data 357 * have to be in the first 64 MB of memory, since this is 358 * the maximum mapped by the Linux kernel during initialization. 359 */ 360 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 361 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 362 363 #if defined(CONFIG_CMD_KGDB) 364 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 365 #endif 366 367 /* 368 * Environment Configuration 369 */ 370 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 371 #define CONFIG_HAS_ETH0 372 #define CONFIG_HAS_ETH1 373 #define CONFIG_HAS_ETH2 374 #define CONFIG_HAS_ETH3 375 #endif 376 377 #define CONFIG_IPADDR 192.168.1.253 378 379 #define CONFIG_HOSTNAME "unknown" 380 #define CONFIG_ROOTPATH "/nfsroot" 381 #define CONFIG_BOOTFILE "your.uImage" 382 383 #define CONFIG_SERVERIP 192.168.1.1 384 #define CONFIG_GATEWAYIP 192.168.1.1 385 #define CONFIG_NETMASK 255.255.255.0 386 387 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 388 389 #define CONFIG_EXTRA_ENV_SETTINGS \ 390 "netdev=eth0\0" \ 391 "consoledev=ttyCPM\0" \ 392 "ramdiskaddr=1000000\0" \ 393 "ramdiskfile=your.ramdisk.u-boot\0" \ 394 "fdtaddr=400000\0" \ 395 "fdtfile=mpc8560ads.dtb\0" 396 397 #define CONFIG_NFSBOOTCOMMAND \ 398 "setenv bootargs root=/dev/nfs rw " \ 399 "nfsroot=$serverip:$rootpath " \ 400 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 401 "console=$consoledev,$baudrate $othbootargs;" \ 402 "tftp $loadaddr $bootfile;" \ 403 "tftp $fdtaddr $fdtfile;" \ 404 "bootm $loadaddr - $fdtaddr" 405 406 #define CONFIG_RAMBOOTCOMMAND \ 407 "setenv bootargs root=/dev/ram rw " \ 408 "console=$consoledev,$baudrate $othbootargs;" \ 409 "tftp $ramdiskaddr $ramdiskfile;" \ 410 "tftp $loadaddr $bootfile;" \ 411 "tftp $fdtaddr $fdtfile;" \ 412 "bootm $loadaddr $ramdiskaddr $fdtaddr" 413 414 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 415 416 #endif /* __CONFIG_H */ 417