1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_CPM2 1 /* has CPM2 */ 25 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 26 #define CONFIG_MPC8560 1 27 28 /* 29 * default CCARBAR is at 0xff700000 30 * assume U-Boot is less than 0.5MB 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0xfff80000 33 34 #define CONFIG_PCI_INDIRECT_BRIDGE 35 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 36 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 37 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 38 #define CONFIG_ENV_OVERWRITE 39 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 40 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 41 42 /* 43 * sysclk for MPC85xx 44 * 45 * Two valid values are: 46 * 33000000 47 * 66000000 48 * 49 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 50 * is likely the desired value here, so that is now the default. 51 * The board, however, can run at 66MHz. In any event, this value 52 * must match the settings of some switches. Details can be found 53 * in the README.mpc85xxads. 54 */ 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #define CONFIG_SYS_CLK_FREQ 33000000 58 #endif 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_L2_CACHE /* toggle L2 cache */ 64 #define CONFIG_BTB /* toggle branch predition */ 65 66 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 67 68 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 69 #define CONFIG_SYS_MEMTEST_END 0x00400000 70 71 #define CONFIG_SYS_CCSRBAR 0xe0000000 72 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 73 74 /* DDR Setup */ 75 #define CONFIG_SYS_FSL_DDR1 76 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 77 #define CONFIG_DDR_SPD 78 #undef CONFIG_FSL_DDR_INTERACTIVE 79 80 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 81 82 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 83 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 84 85 #define CONFIG_NUM_DDR_CONTROLLERS 1 86 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 87 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 88 89 /* I2C addresses of SPD EEPROMs */ 90 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 91 92 /* These are used when DDR doesn't use SPD. */ 93 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 94 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 95 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 96 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 97 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 98 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 99 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 100 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 101 102 /* 103 * SDRAM on the Local Bus 104 */ 105 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 106 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 107 108 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 109 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 110 111 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 112 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 113 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 114 #undef CONFIG_SYS_FLASH_CHECKSUM 115 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 116 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 117 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 119 120 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 121 #define CONFIG_SYS_RAMBOOT 122 #else 123 #undef CONFIG_SYS_RAMBOOT 124 #endif 125 126 #define CONFIG_FLASH_CFI_DRIVER 127 #define CONFIG_SYS_FLASH_CFI 128 #define CONFIG_SYS_FLASH_EMPTY_INFO 129 130 #undef CONFIG_CLOCKS_IN_MHZ 131 132 /* 133 * Local Bus Definitions 134 */ 135 136 /* 137 * Base Register 2 and Option Register 2 configure SDRAM. 138 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 139 * 140 * For BR2, need: 141 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 142 * port-size = 32-bits = BR2[19:20] = 11 143 * no parity checking = BR2[21:22] = 00 144 * SDRAM for MSEL = BR2[24:26] = 011 145 * Valid = BR[31] = 1 146 * 147 * 0 4 8 12 16 20 24 28 148 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 149 * 150 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 151 * FIXME: the top 17 bits of BR2. 152 */ 153 154 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 155 156 /* 157 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 158 * 159 * For OR2, need: 160 * 64MB mask for AM, OR2[0:7] = 1111 1100 161 * XAM, OR2[17:18] = 11 162 * 9 columns OR2[19-21] = 010 163 * 13 rows OR2[23-25] = 100 164 * EAD set for extra time OR[31] = 1 165 * 166 * 0 4 8 12 16 20 24 28 167 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 168 */ 169 170 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 171 172 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 173 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 174 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 175 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 176 177 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 178 | LSDMR_RFCR5 \ 179 | LSDMR_PRETOACT3 \ 180 | LSDMR_ACTTORW3 \ 181 | LSDMR_BL8 \ 182 | LSDMR_WRC2 \ 183 | LSDMR_CL3 \ 184 | LSDMR_RFEN \ 185 ) 186 187 /* 188 * SDRAM Controller configuration sequence. 189 */ 190 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 191 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 192 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 193 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 194 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 195 196 /* 197 * 32KB, 8-bit wide for ADS config reg 198 */ 199 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 200 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 201 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 202 203 #define CONFIG_SYS_INIT_RAM_LOCK 1 204 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 205 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 206 207 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 208 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 209 210 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 211 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 212 213 /* Serial Port */ 214 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 215 #undef CONFIG_CONS_NONE /* define if console on something else */ 216 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 217 218 #define CONFIG_BAUDRATE 115200 219 220 #define CONFIG_SYS_BAUDRATE_TABLE \ 221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 222 223 /* 224 * I2C 225 */ 226 #define CONFIG_SYS_I2C 227 #define CONFIG_SYS_I2C_FSL 228 #define CONFIG_SYS_FSL_I2C_SPEED 400000 229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 230 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 231 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 232 233 /* RapidIO MMU */ 234 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 235 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 236 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 237 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 238 239 /* 240 * General PCI 241 * Memory space is mapped 1-1, but I/O space must start from 0. 242 */ 243 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 244 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 245 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 246 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 247 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 248 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 249 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 250 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 251 252 #if defined(CONFIG_PCI) 253 #undef CONFIG_EEPRO100 254 #undef CONFIG_TULIP 255 256 #if !defined(CONFIG_PCI_PNP) 257 #define PCI_ENET0_IOADDR 0xe0000000 258 #define PCI_ENET0_MEMADDR 0xe0000000 259 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 260 #endif 261 262 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 263 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 264 265 #endif /* CONFIG_PCI */ 266 267 #ifdef CONFIG_TSEC_ENET 268 269 #ifndef CONFIG_MII 270 #define CONFIG_MII 1 /* MII PHY management */ 271 #endif 272 #define CONFIG_TSEC1 1 273 #define CONFIG_TSEC1_NAME "TSEC0" 274 #define CONFIG_TSEC2 1 275 #define CONFIG_TSEC2_NAME "TSEC1" 276 #define TSEC1_PHY_ADDR 0 277 #define TSEC2_PHY_ADDR 1 278 #define TSEC1_PHYIDX 0 279 #define TSEC2_PHYIDX 0 280 #define TSEC1_FLAGS TSEC_GIGABIT 281 #define TSEC2_FLAGS TSEC_GIGABIT 282 283 /* Options are: TSEC[0-1] */ 284 #define CONFIG_ETHPRIME "TSEC0" 285 286 #endif /* CONFIG_TSEC_ENET */ 287 288 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 289 290 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 291 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 292 293 #if (CONFIG_ETHER_INDEX == 2) 294 /* 295 * - Rx-CLK is CLK13 296 * - Tx-CLK is CLK14 297 * - Select bus for bd/buffers 298 * - Full duplex 299 */ 300 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 301 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 302 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 303 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 304 #define FETH2_RST 0x01 305 #elif (CONFIG_ETHER_INDEX == 3) 306 /* need more definitions here for FE3 */ 307 #define FETH3_RST 0x80 308 #endif /* CONFIG_ETHER_INDEX */ 309 310 #ifndef CONFIG_MII 311 #define CONFIG_MII 1 /* MII PHY management */ 312 #endif 313 314 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 315 316 /* 317 * GPIO pins used for bit-banged MII communications 318 */ 319 #define MDIO_PORT 2 /* Port C */ 320 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 321 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 322 #define MDC_DECLARE MDIO_DECLARE 323 324 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 325 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 326 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 327 328 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 329 else iop->pdat &= ~0x00400000 330 331 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 332 else iop->pdat &= ~0x00200000 333 334 #define MIIDELAY udelay(1) 335 336 #endif 337 338 /* 339 * Environment 340 */ 341 #ifndef CONFIG_SYS_RAMBOOT 342 #define CONFIG_ENV_IS_IN_FLASH 1 343 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 344 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 345 #define CONFIG_ENV_SIZE 0x2000 346 #else 347 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 348 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 350 #define CONFIG_ENV_SIZE 0x2000 351 #endif 352 353 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 354 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 355 356 /* 357 * BOOTP options 358 */ 359 #define CONFIG_BOOTP_BOOTFILESIZE 360 #define CONFIG_BOOTP_BOOTPATH 361 #define CONFIG_BOOTP_GATEWAY 362 #define CONFIG_BOOTP_HOSTNAME 363 364 /* 365 * Command line configuration. 366 */ 367 #define CONFIG_CMD_IRQ 368 #define CONFIG_CMD_REGINFO 369 370 #if defined(CONFIG_PCI) 371 #define CONFIG_CMD_PCI 372 #endif 373 374 #if defined(CONFIG_ETHER_ON_FCC) 375 #endif 376 377 #undef CONFIG_WATCHDOG /* watchdog disabled */ 378 379 /* 380 * Miscellaneous configurable options 381 */ 382 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 383 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 384 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 385 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 386 387 #if defined(CONFIG_CMD_KGDB) 388 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 389 #else 390 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 391 #endif 392 393 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 394 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 395 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 396 397 /* 398 * For booting Linux, the board info and command line data 399 * have to be in the first 64 MB of memory, since this is 400 * the maximum mapped by the Linux kernel during initialization. 401 */ 402 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 403 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 404 405 #if defined(CONFIG_CMD_KGDB) 406 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 407 #endif 408 409 /* 410 * Environment Configuration 411 */ 412 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 413 #define CONFIG_HAS_ETH0 414 #define CONFIG_HAS_ETH1 415 #define CONFIG_HAS_ETH2 416 #define CONFIG_HAS_ETH3 417 #endif 418 419 #define CONFIG_IPADDR 192.168.1.253 420 421 #define CONFIG_HOSTNAME unknown 422 #define CONFIG_ROOTPATH "/nfsroot" 423 #define CONFIG_BOOTFILE "your.uImage" 424 425 #define CONFIG_SERVERIP 192.168.1.1 426 #define CONFIG_GATEWAYIP 192.168.1.1 427 #define CONFIG_NETMASK 255.255.255.0 428 429 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 430 431 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 432 433 #define CONFIG_BAUDRATE 115200 434 435 #define CONFIG_EXTRA_ENV_SETTINGS \ 436 "netdev=eth0\0" \ 437 "consoledev=ttyCPM\0" \ 438 "ramdiskaddr=1000000\0" \ 439 "ramdiskfile=your.ramdisk.u-boot\0" \ 440 "fdtaddr=400000\0" \ 441 "fdtfile=mpc8560ads.dtb\0" 442 443 #define CONFIG_NFSBOOTCOMMAND \ 444 "setenv bootargs root=/dev/nfs rw " \ 445 "nfsroot=$serverip:$rootpath " \ 446 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 447 "console=$consoledev,$baudrate $othbootargs;" \ 448 "tftp $loadaddr $bootfile;" \ 449 "tftp $fdtaddr $fdtfile;" \ 450 "bootm $loadaddr - $fdtaddr" 451 452 #define CONFIG_RAMBOOTCOMMAND \ 453 "setenv bootargs root=/dev/ram rw " \ 454 "console=$consoledev,$baudrate $othbootargs;" \ 455 "tftp $ramdiskaddr $ramdiskfile;" \ 456 "tftp $loadaddr $bootfile;" \ 457 "tftp $fdtaddr $fdtfile;" \ 458 "bootm $loadaddr $ramdiskaddr $fdtaddr" 459 460 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 461 462 #endif /* __CONFIG_H */ 463