1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8560ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_CPM2 1 /* has CPM2 */ 42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 43 44 #define CONFIG_PCI 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #undef CONFIG_TSEC_ENET /* tsec ethernet support */ 47 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 48 #define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 49 #define CONFIG_ENV_OVERWRITE 50 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 51 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 52 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 53 54 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 56 57 58 /* 59 * sysclk for MPC85xx 60 * 61 * Two valid values are: 62 * 33000000 63 * 66000000 64 * 65 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 66 * is likely the desired value here, so that is now the default. 67 * The board, however, can run at 66MHz. In any event, this value 68 * must match the settings of some switches. Details can be found 69 * in the README.mpc85xxads. 70 */ 71 72 #ifndef CONFIG_SYS_CLK_FREQ 73 #define CONFIG_SYS_CLK_FREQ 33000000 74 #endif 75 76 77 /* 78 * These can be toggled for performance analysis, otherwise use default. 79 */ 80 #define CONFIG_L2_CACHE /* toggle L2 cache */ 81 #define CONFIG_BTB /* toggle branch predition */ 82 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 83 84 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 85 86 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 87 88 #undef CFG_DRAM_TEST /* memory test, takes time */ 89 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 90 #define CFG_MEMTEST_END 0x00400000 91 92 93 /* 94 * Base addresses -- Note these are effective addresses where the 95 * actual resources get mapped (not physical addresses) 96 */ 97 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 98 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 99 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 100 101 102 /* 103 * DDR Setup 104 */ 105 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 106 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 107 108 #if defined(CONFIG_SPD_EEPROM) 109 /* 110 * Determine DDR configuration from I2C interface. 111 */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 113 114 #else 115 /* 116 * Manually set up DDR parameters 117 */ 118 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 119 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 120 #define CFG_DDR_CS0_CONFIG 0x80000002 121 #define CFG_DDR_TIMING_1 0x37344321 122 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 123 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 124 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 125 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 126 #endif 127 128 129 /* 130 * SDRAM on the Local Bus 131 */ 132 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 133 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 134 135 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 136 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 137 138 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 139 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 140 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 141 #undef CFG_FLASH_CHECKSUM 142 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 143 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 144 145 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 146 147 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 148 #define CFG_RAMBOOT 149 #else 150 #undef CFG_RAMBOOT 151 #endif 152 153 #define CFG_FLASH_CFI_DRIVER 154 #define CFG_FLASH_CFI 155 #define CFG_FLASH_EMPTY_INFO 156 157 #undef CONFIG_CLOCKS_IN_MHZ 158 159 160 /* 161 * Local Bus Definitions 162 */ 163 164 /* 165 * Base Register 2 and Option Register 2 configure SDRAM. 166 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 167 * 168 * For BR2, need: 169 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 170 * port-size = 32-bits = BR2[19:20] = 11 171 * no parity checking = BR2[21:22] = 00 172 * SDRAM for MSEL = BR2[24:26] = 011 173 * Valid = BR[31] = 1 174 * 175 * 0 4 8 12 16 20 24 28 176 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 177 * 178 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 179 * FIXME: the top 17 bits of BR2. 180 */ 181 182 #define CFG_BR2_PRELIM 0xf0001861 183 184 /* 185 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 186 * 187 * For OR2, need: 188 * 64MB mask for AM, OR2[0:7] = 1111 1100 189 * XAM, OR2[17:18] = 11 190 * 9 columns OR2[19-21] = 010 191 * 13 rows OR2[23-25] = 100 192 * EAD set for extra time OR[31] = 1 193 * 194 * 0 4 8 12 16 20 24 28 195 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 196 */ 197 198 #define CFG_OR2_PRELIM 0xfc006901 199 200 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 201 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 202 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 203 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 204 205 /* 206 * LSDMR masks 207 */ 208 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 209 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 210 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 211 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 212 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 213 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 214 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 215 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 216 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 217 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 218 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 219 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 220 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 221 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 222 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 223 224 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 231 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 232 233 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 234 | CFG_LBC_LSDMR_RFCR5 \ 235 | CFG_LBC_LSDMR_PRETOACT3 \ 236 | CFG_LBC_LSDMR_ACTTORW3 \ 237 | CFG_LBC_LSDMR_BL8 \ 238 | CFG_LBC_LSDMR_WRC2 \ 239 | CFG_LBC_LSDMR_CL3 \ 240 | CFG_LBC_LSDMR_RFEN \ 241 ) 242 243 /* 244 * SDRAM Controller configuration sequence. 245 */ 246 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 247 | CFG_LBC_LSDMR_OP_PCHALL) 248 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 249 | CFG_LBC_LSDMR_OP_ARFRSH) 250 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 251 | CFG_LBC_LSDMR_OP_ARFRSH) 252 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 253 | CFG_LBC_LSDMR_OP_MRW) 254 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 255 | CFG_LBC_LSDMR_OP_NORMAL) 256 257 258 /* 259 * 32KB, 8-bit wide for ADS config reg 260 */ 261 #define CFG_BR4_PRELIM 0xf8000801 262 #define CFG_OR4_PRELIM 0xffffe1f1 263 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 264 265 #define CONFIG_L1_INIT_RAM 266 #define CFG_INIT_RAM_LOCK 1 267 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 268 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 269 270 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 271 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 272 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 273 274 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 275 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 276 277 /* Serial Port */ 278 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 279 #undef CONFIG_CONS_NONE /* define if console on something else */ 280 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 281 282 #define CONFIG_BAUDRATE 115200 283 284 #define CFG_BAUDRATE_TABLE \ 285 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 286 287 /* Use the HUSH parser */ 288 #define CFG_HUSH_PARSER 289 #ifdef CFG_HUSH_PARSER 290 #define CFG_PROMPT_HUSH_PS2 "> " 291 #endif 292 293 /* I2C */ 294 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 295 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 296 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 297 #define CFG_I2C_SLAVE 0x7F 298 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 299 300 /* RapidIO MMU */ 301 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 302 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 303 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 304 305 /* 306 * General PCI 307 * Addresses are mapped 1-1. 308 */ 309 #define CFG_PCI1_MEM_BASE 0x80000000 310 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 311 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 312 #define CFG_PCI1_IO_BASE 0xe2000000 313 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 314 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ 315 316 #if defined(CONFIG_PCI) 317 318 #define CONFIG_NET_MULTI 319 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 320 321 #undef CONFIG_EEPRO100 322 #undef CONFIG_TULIP 323 324 #if !defined(CONFIG_PCI_PNP) 325 #define PCI_ENET0_IOADDR 0xe0000000 326 #define PCI_ENET0_MEMADDR 0xe0000000 327 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 328 #endif 329 330 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 331 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 332 333 #endif /* CONFIG_PCI */ 334 335 336 #if defined(CONFIG_TSEC_ENET) 337 338 #ifndef CONFIG_NET_MULTI 339 #define CONFIG_NET_MULTI 1 340 #endif 341 342 #define CONFIG_MII 1 /* MII PHY management */ 343 #define CONFIG_MPC85XX_TSEC1 1 344 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" 345 #define CONFIG_MPC85XX_TSEC2 1 346 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" 347 #undef CONFIG_MPC85XX_FEC 348 #define TSEC1_PHY_ADDR 0 349 #define TSEC2_PHY_ADDR 1 350 #define TSEC1_PHYIDX 0 351 #define TSEC2_PHYIDX 0 352 353 /* Options are: TSEC[0-1] */ 354 #define CONFIG_ETHPRIME "TSEC0" 355 356 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ 357 358 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 359 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 360 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 361 362 #if (CONFIG_ETHER_INDEX == 2) 363 /* 364 * - Rx-CLK is CLK13 365 * - Tx-CLK is CLK14 366 * - Select bus for bd/buffers 367 * - Full duplex 368 */ 369 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 370 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 371 #define CFG_CPMFCR_RAMTYPE 0 372 #define CFG_FCC_PSMR (FCC_PSMR_FDE) 373 #define FETH2_RST 0x01 374 #elif (CONFIG_ETHER_INDEX == 3) 375 /* need more definitions here for FE3 */ 376 #define FETH3_RST 0x80 377 #endif /* CONFIG_ETHER_INDEX */ 378 379 #define CONFIG_MII /* MII PHY management */ 380 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 381 382 /* 383 * GPIO pins used for bit-banged MII communications 384 */ 385 #define MDIO_PORT 2 /* Port C */ 386 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 387 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 388 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 389 390 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 391 else iop->pdat &= ~0x00400000 392 393 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 394 else iop->pdat &= ~0x00200000 395 396 #define MIIDELAY udelay(1) 397 398 #endif 399 400 401 /* 402 * Environment 403 */ 404 #ifndef CFG_RAMBOOT 405 #define CFG_ENV_IS_IN_FLASH 1 406 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 407 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 408 #define CFG_ENV_SIZE 0x2000 409 #else 410 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 411 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 412 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 413 #define CFG_ENV_SIZE 0x2000 414 #endif 415 416 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 417 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 418 419 #if defined(CFG_RAMBOOT) 420 #if defined(CONFIG_PCI) 421 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 422 | CFG_CMD_PING \ 423 | CFG_CMD_PCI \ 424 | CFG_CMD_I2C) \ 425 & \ 426 ~(CFG_CMD_ENV \ 427 | CFG_CMD_LOADS)) 428 #elif defined(CONFIG_TSEC_ENET) 429 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 430 | CFG_CMD_PING \ 431 | CFG_CMD_I2C) \ 432 & ~(CFG_CMD_ENV)) 433 #elif defined(CONFIG_ETHER_ON_FCC) 434 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ 435 | CFG_CMD_MII \ 436 | CFG_CMD_PING \ 437 | CFG_CMD_I2C) \ 438 & ~(CFG_CMD_ENV)) 439 #endif 440 #else 441 #if defined(CONFIG_PCI) 442 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 443 | CFG_CMD_PCI \ 444 | CFG_CMD_PING \ 445 | CFG_CMD_I2C) 446 #elif defined(CONFIG_TSEC_ENET) 447 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 448 | CFG_CMD_PING \ 449 | CFG_CMD_I2C) 450 #elif defined(CONFIG_ETHER_ON_FCC) 451 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ 452 | CFG_CMD_MII \ 453 | CFG_CMD_PING \ 454 | CFG_CMD_I2C) 455 #endif 456 #endif 457 458 #include <cmd_confdefs.h> 459 460 #undef CONFIG_WATCHDOG /* watchdog disabled */ 461 462 /* 463 * Miscellaneous configurable options 464 */ 465 #define CFG_LONGHELP /* undef to save memory */ 466 #define CFG_LOAD_ADDR 0x1000000 /* default load address */ 467 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 468 469 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 470 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 471 #else 472 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 473 #endif 474 475 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 476 #define CFG_MAXARGS 16 /* max number of command args */ 477 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 478 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 479 480 /* 481 * For booting Linux, the board info and command line data 482 * have to be in the first 8 MB of memory, since this is 483 * the maximum mapped by the Linux kernel during initialization. 484 */ 485 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 486 487 /* Cache Configuration */ 488 #define CFG_DCACHE_SIZE 32768 489 #define CFG_CACHELINE_SIZE 32 490 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 491 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 492 #endif 493 494 /* 495 * Internal Definitions 496 * 497 * Boot Flags 498 */ 499 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 500 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 501 502 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) 503 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 504 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 505 #endif 506 507 508 /* 509 * Environment Configuration 510 */ 511 512 /* The mac addresses for all ethernet interface */ 513 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 514 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 515 #define CONFIG_HAS_ETH1 516 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 517 #define CONFIG_HAS_ETH2 518 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 519 #endif 520 521 #define CONFIG_IPADDR 192.168.1.253 522 523 #define CONFIG_HOSTNAME unknown 524 #define CONFIG_ROOTPATH /nfsroot 525 #define CONFIG_BOOTFILE your.uImage 526 527 #define CONFIG_SERVERIP 192.168.1.1 528 #define CONFIG_GATEWAYIP 192.168.1.1 529 #define CONFIG_NETMASK 255.255.255.0 530 531 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 532 533 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 534 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 535 536 #define CONFIG_BAUDRATE 115200 537 538 #define CONFIG_EXTRA_ENV_SETTINGS \ 539 "netdev=eth0\0" \ 540 "consoledev=ttyS0\0" \ 541 "ramdiskaddr=400000\0" \ 542 "ramdiskfile=your.ramdisk.u-boot\0" 543 544 #define CONFIG_NFSBOOTCOMMAND \ 545 "setenv bootargs root=/dev/nfs rw " \ 546 "nfsroot=$serverip:$rootpath " \ 547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 548 "console=$consoledev,$baudrate $othbootargs;" \ 549 "tftp $loadaddr $bootfile;" \ 550 "bootm $loadaddr" 551 552 #define CONFIG_RAMBOOTCOMMAND \ 553 "setenv bootargs root=/dev/ram rw " \ 554 "console=$consoledev,$baudrate $othbootargs;" \ 555 "tftp $ramdiskaddr $ramdiskfile;" \ 556 "tftp $loadaddr $bootfile;" \ 557 "bootm $loadaddr $ramdiskaddr" 558 559 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 560 561 #endif /* __CONFIG_H */ 562