1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8560ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_CPM2 1 /* has CPM2 */ 42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 43 44 #define CONFIG_PCI 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 49 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 50 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 51 52 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 54 55 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 56 57 /* 58 * sysclk for MPC85xx 59 * 60 * Two valid values are: 61 * 33000000 62 * 66000000 63 * 64 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 65 * is likely the desired value here, so that is now the default. 66 * The board, however, can run at 66MHz. In any event, this value 67 * must match the settings of some switches. Details can be found 68 * in the README.mpc85xxads. 69 */ 70 71 #ifndef CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_CLK_FREQ 33000000 73 #endif 74 75 76 /* 77 * These can be toggled for performance analysis, otherwise use default. 78 */ 79 #define CONFIG_L2_CACHE /* toggle L2 cache */ 80 #define CONFIG_BTB /* toggle branch predition */ 81 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 82 83 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 84 85 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 86 87 #undef CFG_DRAM_TEST /* memory test, takes time */ 88 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 89 #define CFG_MEMTEST_END 0x00400000 90 91 92 /* 93 * Base addresses -- Note these are effective addresses where the 94 * actual resources get mapped (not physical addresses) 95 */ 96 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 97 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 98 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 99 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 100 101 102 /* 103 * DDR Setup 104 */ 105 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 106 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 107 108 #if defined(CONFIG_SPD_EEPROM) 109 /* 110 * Determine DDR configuration from I2C interface. 111 */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 113 114 #else 115 /* 116 * Manually set up DDR parameters 117 */ 118 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ 119 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 120 #define CFG_DDR_CS0_CONFIG 0x80000002 121 #define CFG_DDR_TIMING_1 0x37344321 122 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 123 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 124 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 125 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 126 #endif 127 128 129 /* 130 * SDRAM on the Local Bus 131 */ 132 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 133 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 134 135 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 136 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ 137 138 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 139 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 140 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ 141 #undef CFG_FLASH_CHECKSUM 142 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 143 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 144 145 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 146 147 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 148 #define CFG_RAMBOOT 149 #else 150 #undef CFG_RAMBOOT 151 #endif 152 153 #define CFG_FLASH_CFI_DRIVER 154 #define CFG_FLASH_CFI 155 #define CFG_FLASH_EMPTY_INFO 156 157 #undef CONFIG_CLOCKS_IN_MHZ 158 159 160 /* 161 * Local Bus Definitions 162 */ 163 164 /* 165 * Base Register 2 and Option Register 2 configure SDRAM. 166 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 167 * 168 * For BR2, need: 169 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 170 * port-size = 32-bits = BR2[19:20] = 11 171 * no parity checking = BR2[21:22] = 00 172 * SDRAM for MSEL = BR2[24:26] = 011 173 * Valid = BR[31] = 1 174 * 175 * 0 4 8 12 16 20 24 28 176 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 177 * 178 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 179 * FIXME: the top 17 bits of BR2. 180 */ 181 182 #define CFG_BR2_PRELIM 0xf0001861 183 184 /* 185 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 186 * 187 * For OR2, need: 188 * 64MB mask for AM, OR2[0:7] = 1111 1100 189 * XAM, OR2[17:18] = 11 190 * 9 columns OR2[19-21] = 010 191 * 13 rows OR2[23-25] = 100 192 * EAD set for extra time OR[31] = 1 193 * 194 * 0 4 8 12 16 20 24 28 195 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 196 */ 197 198 #define CFG_OR2_PRELIM 0xfc006901 199 200 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 201 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 202 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 203 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 204 205 /* 206 * LSDMR masks 207 */ 208 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 209 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 210 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 211 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) 212 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 213 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) 214 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 215 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) 216 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 217 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 218 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 219 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) 220 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 221 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) 222 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 223 224 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 225 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 231 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 232 233 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ 234 | CFG_LBC_LSDMR_RFCR5 \ 235 | CFG_LBC_LSDMR_PRETOACT3 \ 236 | CFG_LBC_LSDMR_ACTTORW3 \ 237 | CFG_LBC_LSDMR_BL8 \ 238 | CFG_LBC_LSDMR_WRC2 \ 239 | CFG_LBC_LSDMR_CL3 \ 240 | CFG_LBC_LSDMR_RFEN \ 241 ) 242 243 /* 244 * SDRAM Controller configuration sequence. 245 */ 246 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ 247 | CFG_LBC_LSDMR_OP_PCHALL) 248 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ 249 | CFG_LBC_LSDMR_OP_ARFRSH) 250 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ 251 | CFG_LBC_LSDMR_OP_ARFRSH) 252 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ 253 | CFG_LBC_LSDMR_OP_MRW) 254 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ 255 | CFG_LBC_LSDMR_OP_NORMAL) 256 257 258 /* 259 * 32KB, 8-bit wide for ADS config reg 260 */ 261 #define CFG_BR4_PRELIM 0xf8000801 262 #define CFG_OR4_PRELIM 0xffffe1f1 263 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) 264 265 #define CONFIG_L1_INIT_RAM 266 #define CFG_INIT_RAM_LOCK 1 267 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 268 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 269 270 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 271 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 272 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 273 274 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 275 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 276 277 /* Serial Port */ 278 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 279 #undef CONFIG_CONS_NONE /* define if console on something else */ 280 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 281 282 #define CONFIG_BAUDRATE 115200 283 284 #define CFG_BAUDRATE_TABLE \ 285 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 286 287 /* Use the HUSH parser */ 288 #define CFG_HUSH_PARSER 289 #ifdef CFG_HUSH_PARSER 290 #define CFG_PROMPT_HUSH_PS2 "> " 291 #endif 292 293 /* pass open firmware flat tree */ 294 #define CONFIG_OF_LIBFDT 1 295 #define CONFIG_OF_BOARD_SETUP 1 296 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 297 298 /* 299 * I2C 300 */ 301 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 302 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 303 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 304 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 305 #define CFG_I2C_SLAVE 0x7F 306 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 307 #define CFG_I2C_OFFSET 0x3000 308 309 /* RapidIO MMU */ 310 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 311 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 312 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 313 314 /* 315 * General PCI 316 * Memory space is mapped 1-1, but I/O space must start from 0. 317 */ 318 #define CFG_PCI1_MEM_BASE 0x80000000 319 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 320 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 321 #define CFG_PCI1_IO_BASE 0x00000000 322 #define CFG_PCI1_IO_PHYS 0xe2000000 323 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ 324 325 #if defined(CONFIG_PCI) 326 327 #define CONFIG_NET_MULTI 328 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 329 330 #undef CONFIG_EEPRO100 331 #undef CONFIG_TULIP 332 333 #if !defined(CONFIG_PCI_PNP) 334 #define PCI_ENET0_IOADDR 0xe0000000 335 #define PCI_ENET0_MEMADDR 0xe0000000 336 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 337 #endif 338 339 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 340 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 341 342 #endif /* CONFIG_PCI */ 343 344 345 #ifdef CONFIG_TSEC_ENET 346 347 #ifndef CONFIG_NET_MULTI 348 #define CONFIG_NET_MULTI 1 349 #endif 350 351 #ifndef CONFIG_MII 352 #define CONFIG_MII 1 /* MII PHY management */ 353 #endif 354 #define CONFIG_TSEC1 1 355 #define CONFIG_TSEC1_NAME "TSEC0" 356 #define CONFIG_TSEC2 1 357 #define CONFIG_TSEC2_NAME "TSEC1" 358 #define TSEC1_PHY_ADDR 0 359 #define TSEC2_PHY_ADDR 1 360 #define TSEC1_PHYIDX 0 361 #define TSEC2_PHYIDX 0 362 #define TSEC1_FLAGS TSEC_GIGABIT 363 #define TSEC2_FLAGS TSEC_GIGABIT 364 365 /* Options are: TSEC[0-1] */ 366 #define CONFIG_ETHPRIME "TSEC0" 367 368 #endif /* CONFIG_TSEC_ENET */ 369 370 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 371 372 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 373 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 374 375 #if (CONFIG_ETHER_INDEX == 2) 376 /* 377 * - Rx-CLK is CLK13 378 * - Tx-CLK is CLK14 379 * - Select bus for bd/buffers 380 * - Full duplex 381 */ 382 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 383 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 384 #define CFG_CPMFCR_RAMTYPE 0 385 #define CFG_FCC_PSMR (FCC_PSMR_FDE) 386 #define FETH2_RST 0x01 387 #elif (CONFIG_ETHER_INDEX == 3) 388 /* need more definitions here for FE3 */ 389 #define FETH3_RST 0x80 390 #endif /* CONFIG_ETHER_INDEX */ 391 392 #ifndef CONFIG_MII 393 #define CONFIG_MII 1 /* MII PHY management */ 394 #endif 395 396 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 397 398 /* 399 * GPIO pins used for bit-banged MII communications 400 */ 401 #define MDIO_PORT 2 /* Port C */ 402 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 403 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 404 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 405 406 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 407 else iop->pdat &= ~0x00400000 408 409 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 410 else iop->pdat &= ~0x00200000 411 412 #define MIIDELAY udelay(1) 413 414 #endif 415 416 417 /* 418 * Environment 419 */ 420 #ifndef CFG_RAMBOOT 421 #define CFG_ENV_IS_IN_FLASH 1 422 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 423 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 424 #define CFG_ENV_SIZE 0x2000 425 #else 426 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 427 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 428 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 429 #define CFG_ENV_SIZE 0x2000 430 #endif 431 432 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 433 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 434 435 /* 436 * BOOTP options 437 */ 438 #define CONFIG_BOOTP_BOOTFILESIZE 439 #define CONFIG_BOOTP_BOOTPATH 440 #define CONFIG_BOOTP_GATEWAY 441 #define CONFIG_BOOTP_HOSTNAME 442 443 444 /* 445 * Command line configuration. 446 */ 447 #include <config_cmd_default.h> 448 449 #define CONFIG_CMD_PING 450 #define CONFIG_CMD_I2C 451 #define CONFIG_CMD_ELF 452 453 #if defined(CONFIG_PCI) 454 #define CONFIG_CMD_PCI 455 #endif 456 457 #if defined(CONFIG_ETHER_ON_FCC) 458 #define CONFIG_CMD_MII 459 #endif 460 461 #if defined(CFG_RAMBOOT) 462 #undef CONFIG_CMD_ENV 463 #undef CONFIG_CMD_LOADS 464 #endif 465 466 467 #undef CONFIG_WATCHDOG /* watchdog disabled */ 468 469 /* 470 * Miscellaneous configurable options 471 */ 472 #define CFG_LONGHELP /* undef to save memory */ 473 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 474 #define CFG_LOAD_ADDR 0x1000000 /* default load address */ 475 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 476 477 #if defined(CONFIG_CMD_KGDB) 478 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 479 #else 480 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 481 #endif 482 483 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 484 #define CFG_MAXARGS 16 /* max number of command args */ 485 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 486 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 487 488 /* 489 * For booting Linux, the board info and command line data 490 * have to be in the first 8 MB of memory, since this is 491 * the maximum mapped by the Linux kernel during initialization. 492 */ 493 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 494 495 /* 496 * Internal Definitions 497 * 498 * Boot Flags 499 */ 500 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 501 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 502 503 #if defined(CONFIG_CMD_KGDB) 504 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 505 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 506 #endif 507 508 509 /* 510 * Environment Configuration 511 */ 512 513 /* The mac addresses for all ethernet interface */ 514 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 515 #define CONFIG_HAS_ETH0 516 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 517 #define CONFIG_HAS_ETH1 518 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 519 #define CONFIG_HAS_ETH2 520 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 521 #define CONFIG_HAS_ETH3 522 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 523 #endif 524 525 #define CONFIG_IPADDR 192.168.1.253 526 527 #define CONFIG_HOSTNAME unknown 528 #define CONFIG_ROOTPATH /nfsroot 529 #define CONFIG_BOOTFILE your.uImage 530 531 #define CONFIG_SERVERIP 192.168.1.1 532 #define CONFIG_GATEWAYIP 192.168.1.1 533 #define CONFIG_NETMASK 255.255.255.0 534 535 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 536 537 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 538 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 539 540 #define CONFIG_BAUDRATE 115200 541 542 #define CONFIG_EXTRA_ENV_SETTINGS \ 543 "netdev=eth0\0" \ 544 "consoledev=ttyCPM\0" \ 545 "ramdiskaddr=1000000\0" \ 546 "ramdiskfile=your.ramdisk.u-boot\0" \ 547 "fdtaddr=400000\0" \ 548 "fdtfile=mpc8560ads.dtb\0" 549 550 #define CONFIG_NFSBOOTCOMMAND \ 551 "setenv bootargs root=/dev/nfs rw " \ 552 "nfsroot=$serverip:$rootpath " \ 553 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 554 "console=$consoledev,$baudrate $othbootargs;" \ 555 "tftp $loadaddr $bootfile;" \ 556 "tftp $fdtaddr $fdtfile;" \ 557 "bootm $loadaddr - $fdtaddr" 558 559 #define CONFIG_RAMBOOTCOMMAND \ 560 "setenv bootargs root=/dev/ram rw " \ 561 "console=$consoledev,$baudrate $othbootargs;" \ 562 "tftp $ramdiskaddr $ramdiskfile;" \ 563 "tftp $loadaddr $bootfile;" \ 564 "tftp $fdtaddr $fdtfile;" \ 565 "bootm $loadaddr $ramdiskaddr $fdtaddr" 566 567 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 568 569 #endif /* __CONFIG_H */ 570