1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * mpc8560ads board configuration file 11 * 12 * Please refer to doc/README.mpc85xx for more info. 13 * 14 * Make sure you change the MAC address and other network params first, 15 * search for CONFIG_SERVERIP, etc. in this file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 1 /* BOOKE */ 23 #define CONFIG_E500 1 /* BOOKE e500 family */ 24 #define CONFIG_CPM2 1 /* has CPM2 */ 25 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ 26 #define CONFIG_MPC8560 1 27 28 /* 29 * default CCARBAR is at 0xff700000 30 * assume U-Boot is less than 0.5MB 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0xfff80000 33 34 #define CONFIG_PCI 35 #define CONFIG_PCI_INDIRECT_BRIDGE 36 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 37 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 38 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 39 #define CONFIG_ENV_OVERWRITE 40 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 41 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 42 43 /* 44 * sysclk for MPC85xx 45 * 46 * Two valid values are: 47 * 33000000 48 * 66000000 49 * 50 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 51 * is likely the desired value here, so that is now the default. 52 * The board, however, can run at 66MHz. In any event, this value 53 * must match the settings of some switches. Details can be found 54 * in the README.mpc85xxads. 55 */ 56 57 #ifndef CONFIG_SYS_CLK_FREQ 58 #define CONFIG_SYS_CLK_FREQ 33000000 59 #endif 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* toggle branch predition */ 66 67 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 68 69 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 70 #define CONFIG_SYS_MEMTEST_END 0x00400000 71 72 #define CONFIG_SYS_CCSRBAR 0xe0000000 73 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 74 75 /* DDR Setup */ 76 #define CONFIG_SYS_FSL_DDR1 77 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 78 #define CONFIG_DDR_SPD 79 #undef CONFIG_FSL_DDR_INTERACTIVE 80 81 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 82 83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 85 86 #define CONFIG_NUM_DDR_CONTROLLERS 1 87 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 88 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 89 90 /* I2C addresses of SPD EEPROMs */ 91 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 92 93 /* These are used when DDR doesn't use SPD. */ 94 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 95 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 96 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 97 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 99 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 100 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 101 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 102 103 /* 104 * SDRAM on the Local Bus 105 */ 106 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 107 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 108 109 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 110 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 111 112 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 113 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 114 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 115 #undef CONFIG_SYS_FLASH_CHECKSUM 116 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 118 119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 120 121 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 122 #define CONFIG_SYS_RAMBOOT 123 #else 124 #undef CONFIG_SYS_RAMBOOT 125 #endif 126 127 #define CONFIG_FLASH_CFI_DRIVER 128 #define CONFIG_SYS_FLASH_CFI 129 #define CONFIG_SYS_FLASH_EMPTY_INFO 130 131 #undef CONFIG_CLOCKS_IN_MHZ 132 133 /* 134 * Local Bus Definitions 135 */ 136 137 /* 138 * Base Register 2 and Option Register 2 configure SDRAM. 139 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 140 * 141 * For BR2, need: 142 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 143 * port-size = 32-bits = BR2[19:20] = 11 144 * no parity checking = BR2[21:22] = 00 145 * SDRAM for MSEL = BR2[24:26] = 011 146 * Valid = BR[31] = 1 147 * 148 * 0 4 8 12 16 20 24 28 149 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 150 * 151 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 152 * FIXME: the top 17 bits of BR2. 153 */ 154 155 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 156 157 /* 158 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 159 * 160 * For OR2, need: 161 * 64MB mask for AM, OR2[0:7] = 1111 1100 162 * XAM, OR2[17:18] = 11 163 * 9 columns OR2[19-21] = 010 164 * 13 rows OR2[23-25] = 100 165 * EAD set for extra time OR[31] = 1 166 * 167 * 0 4 8 12 16 20 24 28 168 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 169 */ 170 171 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 172 173 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 174 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 175 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 176 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 177 178 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 179 | LSDMR_RFCR5 \ 180 | LSDMR_PRETOACT3 \ 181 | LSDMR_ACTTORW3 \ 182 | LSDMR_BL8 \ 183 | LSDMR_WRC2 \ 184 | LSDMR_CL3 \ 185 | LSDMR_RFEN \ 186 ) 187 188 /* 189 * SDRAM Controller configuration sequence. 190 */ 191 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 192 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 193 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 194 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 195 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 196 197 /* 198 * 32KB, 8-bit wide for ADS config reg 199 */ 200 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 201 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 202 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 203 204 #define CONFIG_SYS_INIT_RAM_LOCK 1 205 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 206 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 207 208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 210 211 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 212 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 213 214 /* Serial Port */ 215 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 216 #undef CONFIG_CONS_NONE /* define if console on something else */ 217 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 218 219 #define CONFIG_BAUDRATE 115200 220 221 #define CONFIG_SYS_BAUDRATE_TABLE \ 222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 223 224 /* 225 * I2C 226 */ 227 #define CONFIG_SYS_I2C 228 #define CONFIG_SYS_I2C_FSL 229 #define CONFIG_SYS_FSL_I2C_SPEED 400000 230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 232 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 233 234 /* RapidIO MMU */ 235 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 236 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 237 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 238 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 239 240 /* 241 * General PCI 242 * Memory space is mapped 1-1, but I/O space must start from 0. 243 */ 244 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 245 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 246 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 247 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 248 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 249 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 251 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 252 253 #if defined(CONFIG_PCI) 254 255 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 256 257 #undef CONFIG_EEPRO100 258 #undef CONFIG_TULIP 259 260 #if !defined(CONFIG_PCI_PNP) 261 #define PCI_ENET0_IOADDR 0xe0000000 262 #define PCI_ENET0_MEMADDR 0xe0000000 263 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 264 #endif 265 266 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 267 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 268 269 #endif /* CONFIG_PCI */ 270 271 #ifdef CONFIG_TSEC_ENET 272 273 #ifndef CONFIG_MII 274 #define CONFIG_MII 1 /* MII PHY management */ 275 #endif 276 #define CONFIG_TSEC1 1 277 #define CONFIG_TSEC1_NAME "TSEC0" 278 #define CONFIG_TSEC2 1 279 #define CONFIG_TSEC2_NAME "TSEC1" 280 #define TSEC1_PHY_ADDR 0 281 #define TSEC2_PHY_ADDR 1 282 #define TSEC1_PHYIDX 0 283 #define TSEC2_PHYIDX 0 284 #define TSEC1_FLAGS TSEC_GIGABIT 285 #define TSEC2_FLAGS TSEC_GIGABIT 286 287 /* Options are: TSEC[0-1] */ 288 #define CONFIG_ETHPRIME "TSEC0" 289 290 #endif /* CONFIG_TSEC_ENET */ 291 292 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 293 294 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 295 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 296 297 #if (CONFIG_ETHER_INDEX == 2) 298 /* 299 * - Rx-CLK is CLK13 300 * - Tx-CLK is CLK14 301 * - Select bus for bd/buffers 302 * - Full duplex 303 */ 304 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 305 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 306 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 307 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 308 #define FETH2_RST 0x01 309 #elif (CONFIG_ETHER_INDEX == 3) 310 /* need more definitions here for FE3 */ 311 #define FETH3_RST 0x80 312 #endif /* CONFIG_ETHER_INDEX */ 313 314 #ifndef CONFIG_MII 315 #define CONFIG_MII 1 /* MII PHY management */ 316 #endif 317 318 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 319 320 /* 321 * GPIO pins used for bit-banged MII communications 322 */ 323 #define MDIO_PORT 2 /* Port C */ 324 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 325 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 326 #define MDC_DECLARE MDIO_DECLARE 327 328 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 329 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 330 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 331 332 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 333 else iop->pdat &= ~0x00400000 334 335 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 336 else iop->pdat &= ~0x00200000 337 338 #define MIIDELAY udelay(1) 339 340 #endif 341 342 /* 343 * Environment 344 */ 345 #ifndef CONFIG_SYS_RAMBOOT 346 #define CONFIG_ENV_IS_IN_FLASH 1 347 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 348 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 349 #define CONFIG_ENV_SIZE 0x2000 350 #else 351 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 352 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 353 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 354 #define CONFIG_ENV_SIZE 0x2000 355 #endif 356 357 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 358 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 359 360 /* 361 * BOOTP options 362 */ 363 #define CONFIG_BOOTP_BOOTFILESIZE 364 #define CONFIG_BOOTP_BOOTPATH 365 #define CONFIG_BOOTP_GATEWAY 366 #define CONFIG_BOOTP_HOSTNAME 367 368 /* 369 * Command line configuration. 370 */ 371 #define CONFIG_CMD_IRQ 372 #define CONFIG_CMD_REGINFO 373 374 #if defined(CONFIG_PCI) 375 #define CONFIG_CMD_PCI 376 #endif 377 378 #if defined(CONFIG_ETHER_ON_FCC) 379 #endif 380 381 #undef CONFIG_WATCHDOG /* watchdog disabled */ 382 383 /* 384 * Miscellaneous configurable options 385 */ 386 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 387 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 388 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 389 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 390 391 #if defined(CONFIG_CMD_KGDB) 392 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 393 #else 394 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 395 #endif 396 397 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 398 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 399 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 400 401 /* 402 * For booting Linux, the board info and command line data 403 * have to be in the first 64 MB of memory, since this is 404 * the maximum mapped by the Linux kernel during initialization. 405 */ 406 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 407 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 408 409 #if defined(CONFIG_CMD_KGDB) 410 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 411 #endif 412 413 /* 414 * Environment Configuration 415 */ 416 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 417 #define CONFIG_HAS_ETH0 418 #define CONFIG_HAS_ETH1 419 #define CONFIG_HAS_ETH2 420 #define CONFIG_HAS_ETH3 421 #endif 422 423 #define CONFIG_IPADDR 192.168.1.253 424 425 #define CONFIG_HOSTNAME unknown 426 #define CONFIG_ROOTPATH "/nfsroot" 427 #define CONFIG_BOOTFILE "your.uImage" 428 429 #define CONFIG_SERVERIP 192.168.1.1 430 #define CONFIG_GATEWAYIP 192.168.1.1 431 #define CONFIG_NETMASK 255.255.255.0 432 433 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 434 435 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 436 437 #define CONFIG_BAUDRATE 115200 438 439 #define CONFIG_EXTRA_ENV_SETTINGS \ 440 "netdev=eth0\0" \ 441 "consoledev=ttyCPM\0" \ 442 "ramdiskaddr=1000000\0" \ 443 "ramdiskfile=your.ramdisk.u-boot\0" \ 444 "fdtaddr=400000\0" \ 445 "fdtfile=mpc8560ads.dtb\0" 446 447 #define CONFIG_NFSBOOTCOMMAND \ 448 "setenv bootargs root=/dev/nfs rw " \ 449 "nfsroot=$serverip:$rootpath " \ 450 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 451 "console=$consoledev,$baudrate $othbootargs;" \ 452 "tftp $loadaddr $bootfile;" \ 453 "tftp $fdtaddr $fdtfile;" \ 454 "bootm $loadaddr - $fdtaddr" 455 456 #define CONFIG_RAMBOOTCOMMAND \ 457 "setenv bootargs root=/dev/ram rw " \ 458 "console=$consoledev,$baudrate $othbootargs;" \ 459 "tftp $ramdiskaddr $ramdiskfile;" \ 460 "tftp $loadaddr $bootfile;" \ 461 "tftp $fdtaddr $fdtfile;" \ 462 "bootm $loadaddr $ramdiskaddr $fdtaddr" 463 464 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 465 466 #endif /* __CONFIG_H */ 467