1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8555cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 /* High Level Configuration Options */ 19 #define CONFIG_BOOKE 1 /* BOOKE */ 20 #define CONFIG_E500 1 /* BOOKE e500 family */ 21 #define CONFIG_CPM2 1 /* has CPM2 */ 22 #define CONFIG_MPC8555 1 /* MPC8555 specific */ 23 #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ 24 25 #define CONFIG_SYS_TEXT_BASE 0xfff80000 26 27 #define CONFIG_PCI 28 #define CONFIG_PCI_INDIRECT_BRIDGE 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 31 #define CONFIG_ENV_OVERWRITE 32 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 33 34 #define CONFIG_FSL_VIA 35 36 37 #ifndef __ASSEMBLY__ 38 extern unsigned long get_clock_freq(void); 39 #endif 40 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 41 42 /* 43 * These can be toggled for performance analysis, otherwise use default. 44 */ 45 #define CONFIG_L2_CACHE /* toggle L2 cache */ 46 #define CONFIG_BTB /* toggle branch predition */ 47 48 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 49 #define CONFIG_SYS_MEMTEST_END 0x00400000 50 51 #define CONFIG_SYS_CCSRBAR 0xe0000000 52 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 53 54 /* DDR Setup */ 55 #define CONFIG_SYS_FSL_DDR1 56 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 57 #define CONFIG_DDR_SPD 58 #undef CONFIG_FSL_DDR_INTERACTIVE 59 60 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 61 62 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 63 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 64 65 #define CONFIG_NUM_DDR_CONTROLLERS 1 66 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 67 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 68 69 /* I2C addresses of SPD EEPROMs */ 70 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 71 72 /* Make sure required options are set */ 73 #ifndef CONFIG_SPD_EEPROM 74 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 75 #endif 76 77 #undef CONFIG_CLOCKS_IN_MHZ 78 79 /* 80 * Local Bus Definitions 81 */ 82 83 /* 84 * FLASH on the Local Bus 85 * Two banks, 8M each, using the CFI driver. 86 * Boot from BR0/OR0 bank at 0xff00_0000 87 * Alternate BR1/OR1 bank at 0xff80_0000 88 * 89 * BR0, BR1: 90 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 91 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 92 * Port Size = 16 bits = BRx[19:20] = 10 93 * Use GPCM = BRx[24:26] = 000 94 * Valid = BRx[31] = 1 95 * 96 * 0 4 8 12 16 20 24 28 97 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 98 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 99 * 100 * OR0, OR1: 101 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 102 * Reserved ORx[17:18] = 11, confusion here? 103 * CSNT = ORx[20] = 1 104 * ACS = half cycle delay = ORx[21:22] = 11 105 * SCY = 6 = ORx[24:27] = 0110 106 * TRLX = use relaxed timing = ORx[29] = 1 107 * EAD = use external address latch delay = OR[31] = 1 108 * 109 * 0 4 8 12 16 20 24 28 110 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 111 */ 112 113 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 114 115 #define CONFIG_SYS_BR0_PRELIM 0xff801001 116 #define CONFIG_SYS_BR1_PRELIM 0xff001001 117 118 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 119 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 120 121 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 122 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 123 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 124 #undef CONFIG_SYS_FLASH_CHECKSUM 125 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 126 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 127 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 129 130 #define CONFIG_FLASH_CFI_DRIVER 131 #define CONFIG_SYS_FLASH_CFI 132 #define CONFIG_SYS_FLASH_EMPTY_INFO 133 134 135 /* 136 * SDRAM on the Local Bus 137 */ 138 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 139 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 140 141 /* 142 * Base Register 2 and Option Register 2 configure SDRAM. 143 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 144 * 145 * For BR2, need: 146 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 147 * port-size = 32-bits = BR2[19:20] = 11 148 * no parity checking = BR2[21:22] = 00 149 * SDRAM for MSEL = BR2[24:26] = 011 150 * Valid = BR[31] = 1 151 * 152 * 0 4 8 12 16 20 24 28 153 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 154 * 155 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 156 * FIXME: the top 17 bits of BR2. 157 */ 158 159 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 160 161 /* 162 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 163 * 164 * For OR2, need: 165 * 64MB mask for AM, OR2[0:7] = 1111 1100 166 * XAM, OR2[17:18] = 11 167 * 9 columns OR2[19-21] = 010 168 * 13 rows OR2[23-25] = 100 169 * EAD set for extra time OR[31] = 1 170 * 171 * 0 4 8 12 16 20 24 28 172 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 173 */ 174 175 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 176 177 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 178 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 179 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 180 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 181 182 /* 183 * Common settings for all Local Bus SDRAM commands. 184 * At run time, either BSMA1516 (for CPU 1.1) 185 * or BSMA1617 (for CPU 1.0) (old) 186 * is OR'ed in too. 187 */ 188 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 189 | LSDMR_PRETOACT7 \ 190 | LSDMR_ACTTORW7 \ 191 | LSDMR_BL8 \ 192 | LSDMR_WRC4 \ 193 | LSDMR_CL3 \ 194 | LSDMR_RFEN \ 195 ) 196 197 /* 198 * The CADMUS registers are connected to CS3 on CDS. 199 * The new memory map places CADMUS at 0xf8000000. 200 * 201 * For BR3, need: 202 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 203 * port-size = 8-bits = BR[19:20] = 01 204 * no parity checking = BR[21:22] = 00 205 * GPMC for MSEL = BR[24:26] = 000 206 * Valid = BR[31] = 1 207 * 208 * 0 4 8 12 16 20 24 28 209 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 210 * 211 * For OR3, need: 212 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 213 * disable buffer ctrl OR[19] = 0 214 * CSNT OR[20] = 1 215 * ACS OR[21:22] = 11 216 * XACS OR[23] = 1 217 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 218 * SETA OR[28] = 0 219 * TRLX OR[29] = 1 220 * EHTR OR[30] = 1 221 * EAD extra time OR[31] = 1 222 * 223 * 0 4 8 12 16 20 24 28 224 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 225 */ 226 227 #define CONFIG_FSL_CADMUS 228 229 #define CADMUS_BASE_ADDR 0xf8000000 230 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 231 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 232 233 #define CONFIG_SYS_INIT_RAM_LOCK 1 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 235 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 236 237 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 238 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 239 240 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 241 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 242 243 /* Serial Port */ 244 #define CONFIG_CONS_INDEX 2 245 #define CONFIG_SYS_NS16550_SERIAL 246 #define CONFIG_SYS_NS16550_REG_SIZE 1 247 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 248 249 #define CONFIG_SYS_BAUDRATE_TABLE \ 250 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 251 252 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 253 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 254 255 /* Use the HUSH parser */ 256 #define CONFIG_SYS_HUSH_PARSER 257 #ifdef CONFIG_SYS_HUSH_PARSER 258 #endif 259 260 /* 261 * I2C 262 */ 263 #define CONFIG_SYS_I2C 264 #define CONFIG_SYS_I2C_FSL 265 #define CONFIG_SYS_FSL_I2C_SPEED 400000 266 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 267 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 268 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 269 270 /* EEPROM */ 271 #define CONFIG_ID_EEPROM 272 #define CONFIG_SYS_I2C_EEPROM_CCID 273 #define CONFIG_SYS_ID_EEPROM 274 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 275 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 276 277 /* 278 * General PCI 279 * Addresses are mapped 1-1. 280 */ 281 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 282 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 283 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 284 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 285 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 286 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 287 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 288 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 289 290 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 291 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 292 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 293 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 294 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 295 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 296 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 297 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 298 299 #ifdef CONFIG_LEGACY 300 #define BRIDGE_ID 17 301 #define VIA_ID 2 302 #else 303 #define BRIDGE_ID 28 304 #define VIA_ID 4 305 #endif 306 307 #if defined(CONFIG_PCI) 308 309 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 310 #define CONFIG_MPC85XX_PCI2 311 312 #undef CONFIG_EEPRO100 313 #undef CONFIG_TULIP 314 315 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 316 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 317 318 #endif /* CONFIG_PCI */ 319 320 321 #if defined(CONFIG_TSEC_ENET) 322 323 #define CONFIG_MII 1 /* MII PHY management */ 324 #define CONFIG_TSEC1 1 325 #define CONFIG_TSEC1_NAME "TSEC0" 326 #define CONFIG_TSEC2 1 327 #define CONFIG_TSEC2_NAME "TSEC1" 328 #define TSEC1_PHY_ADDR 0 329 #define TSEC2_PHY_ADDR 1 330 #define TSEC1_PHYIDX 0 331 #define TSEC2_PHYIDX 0 332 #define TSEC1_FLAGS TSEC_GIGABIT 333 #define TSEC2_FLAGS TSEC_GIGABIT 334 335 /* Options are: TSEC[0-1] */ 336 #define CONFIG_ETHPRIME "TSEC0" 337 338 #endif /* CONFIG_TSEC_ENET */ 339 340 /* 341 * Environment 342 */ 343 #define CONFIG_ENV_IS_IN_FLASH 1 344 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 345 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 346 #define CONFIG_ENV_SIZE 0x2000 347 348 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 349 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 350 351 /* 352 * BOOTP options 353 */ 354 #define CONFIG_BOOTP_BOOTFILESIZE 355 #define CONFIG_BOOTP_BOOTPATH 356 #define CONFIG_BOOTP_GATEWAY 357 #define CONFIG_BOOTP_HOSTNAME 358 359 360 /* 361 * Command line configuration. 362 */ 363 #define CONFIG_CMD_PING 364 #define CONFIG_CMD_I2C 365 #define CONFIG_CMD_MII 366 #define CONFIG_CMD_IRQ 367 #define CONFIG_CMD_REGINFO 368 369 #if defined(CONFIG_PCI) 370 #define CONFIG_CMD_PCI 371 #endif 372 373 374 #undef CONFIG_WATCHDOG /* watchdog disabled */ 375 376 /* 377 * Miscellaneous configurable options 378 */ 379 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 380 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 381 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 382 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 383 #if defined(CONFIG_CMD_KGDB) 384 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 385 #else 386 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 387 #endif 388 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 389 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 390 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 391 392 /* 393 * For booting Linux, the board info and command line data 394 * have to be in the first 64 MB of memory, since this is 395 * the maximum mapped by the Linux kernel during initialization. 396 */ 397 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 398 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 399 400 #if defined(CONFIG_CMD_KGDB) 401 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 402 #endif 403 404 /* 405 * Environment Configuration 406 */ 407 #if defined(CONFIG_TSEC_ENET) 408 #define CONFIG_HAS_ETH0 409 #define CONFIG_HAS_ETH1 410 #define CONFIG_HAS_ETH2 411 #endif 412 413 #define CONFIG_IPADDR 192.168.1.253 414 415 #define CONFIG_HOSTNAME unknown 416 #define CONFIG_ROOTPATH "/nfsroot" 417 #define CONFIG_BOOTFILE "your.uImage" 418 419 #define CONFIG_SERVERIP 192.168.1.1 420 #define CONFIG_GATEWAYIP 192.168.1.1 421 #define CONFIG_NETMASK 255.255.255.0 422 423 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 424 425 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 426 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 427 428 #define CONFIG_BAUDRATE 115200 429 430 #define CONFIG_EXTRA_ENV_SETTINGS \ 431 "netdev=eth0\0" \ 432 "consoledev=ttyS1\0" \ 433 "ramdiskaddr=600000\0" \ 434 "ramdiskfile=your.ramdisk.u-boot\0" \ 435 "fdtaddr=400000\0" \ 436 "fdtfile=your.fdt.dtb\0" 437 438 #define CONFIG_NFSBOOTCOMMAND \ 439 "setenv bootargs root=/dev/nfs rw " \ 440 "nfsroot=$serverip:$rootpath " \ 441 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 442 "console=$consoledev,$baudrate $othbootargs;" \ 443 "tftp $loadaddr $bootfile;" \ 444 "tftp $fdtaddr $fdtfile;" \ 445 "bootm $loadaddr - $fdtaddr" 446 447 #define CONFIG_RAMBOOTCOMMAND \ 448 "setenv bootargs root=/dev/ram rw " \ 449 "console=$consoledev,$baudrate $othbootargs;" \ 450 "tftp $ramdiskaddr $ramdiskfile;" \ 451 "tftp $loadaddr $bootfile;" \ 452 "bootm $loadaddr $ramdiskaddr" 453 454 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 455 456 #endif /* __CONFIG_H */ 457