1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8555cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_CPM2 1 /* has CPM2 */ 18 19 #define CONFIG_PCI_INDIRECT_BRIDGE 20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 21 #define CONFIG_ENV_OVERWRITE 22 23 #define CONFIG_FSL_VIA 24 25 #ifndef __ASSEMBLY__ 26 extern unsigned long get_clock_freq(void); 27 #endif 28 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 29 30 /* 31 * These can be toggled for performance analysis, otherwise use default. 32 */ 33 #define CONFIG_L2_CACHE /* toggle L2 cache */ 34 #define CONFIG_BTB /* toggle branch predition */ 35 36 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 37 #define CONFIG_SYS_MEMTEST_END 0x00400000 38 39 #define CONFIG_SYS_CCSRBAR 0xe0000000 40 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 41 42 /* DDR Setup */ 43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 44 #define CONFIG_DDR_SPD 45 #undef CONFIG_FSL_DDR_INTERACTIVE 46 47 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 48 49 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 50 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 51 52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 53 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 54 55 /* I2C addresses of SPD EEPROMs */ 56 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 57 58 /* Make sure required options are set */ 59 #ifndef CONFIG_SPD_EEPROM 60 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 61 #endif 62 63 #undef CONFIG_CLOCKS_IN_MHZ 64 65 /* 66 * Local Bus Definitions 67 */ 68 69 /* 70 * FLASH on the Local Bus 71 * Two banks, 8M each, using the CFI driver. 72 * Boot from BR0/OR0 bank at 0xff00_0000 73 * Alternate BR1/OR1 bank at 0xff80_0000 74 * 75 * BR0, BR1: 76 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 77 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 78 * Port Size = 16 bits = BRx[19:20] = 10 79 * Use GPCM = BRx[24:26] = 000 80 * Valid = BRx[31] = 1 81 * 82 * 0 4 8 12 16 20 24 28 83 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 84 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 85 * 86 * OR0, OR1: 87 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 88 * Reserved ORx[17:18] = 11, confusion here? 89 * CSNT = ORx[20] = 1 90 * ACS = half cycle delay = ORx[21:22] = 11 91 * SCY = 6 = ORx[24:27] = 0110 92 * TRLX = use relaxed timing = ORx[29] = 1 93 * EAD = use external address latch delay = OR[31] = 1 94 * 95 * 0 4 8 12 16 20 24 28 96 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 97 */ 98 99 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 100 101 #define CONFIG_SYS_BR0_PRELIM 0xff801001 102 #define CONFIG_SYS_BR1_PRELIM 0xff001001 103 104 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 105 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 106 107 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 110 #undef CONFIG_SYS_FLASH_CHECKSUM 111 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 112 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 113 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 115 116 #define CONFIG_FLASH_CFI_DRIVER 117 #define CONFIG_SYS_FLASH_CFI 118 #define CONFIG_SYS_FLASH_EMPTY_INFO 119 120 /* 121 * SDRAM on the Local Bus 122 */ 123 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 124 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 125 126 /* 127 * Base Register 2 and Option Register 2 configure SDRAM. 128 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 129 * 130 * For BR2, need: 131 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 132 * port-size = 32-bits = BR2[19:20] = 11 133 * no parity checking = BR2[21:22] = 00 134 * SDRAM for MSEL = BR2[24:26] = 011 135 * Valid = BR[31] = 1 136 * 137 * 0 4 8 12 16 20 24 28 138 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 139 * 140 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 141 * FIXME: the top 17 bits of BR2. 142 */ 143 144 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 145 146 /* 147 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 148 * 149 * For OR2, need: 150 * 64MB mask for AM, OR2[0:7] = 1111 1100 151 * XAM, OR2[17:18] = 11 152 * 9 columns OR2[19-21] = 010 153 * 13 rows OR2[23-25] = 100 154 * EAD set for extra time OR[31] = 1 155 * 156 * 0 4 8 12 16 20 24 28 157 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 158 */ 159 160 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 161 162 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 163 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 164 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 165 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 166 167 /* 168 * Common settings for all Local Bus SDRAM commands. 169 * At run time, either BSMA1516 (for CPU 1.1) 170 * or BSMA1617 (for CPU 1.0) (old) 171 * is OR'ed in too. 172 */ 173 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 174 | LSDMR_PRETOACT7 \ 175 | LSDMR_ACTTORW7 \ 176 | LSDMR_BL8 \ 177 | LSDMR_WRC4 \ 178 | LSDMR_CL3 \ 179 | LSDMR_RFEN \ 180 ) 181 182 /* 183 * The CADMUS registers are connected to CS3 on CDS. 184 * The new memory map places CADMUS at 0xf8000000. 185 * 186 * For BR3, need: 187 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 188 * port-size = 8-bits = BR[19:20] = 01 189 * no parity checking = BR[21:22] = 00 190 * GPMC for MSEL = BR[24:26] = 000 191 * Valid = BR[31] = 1 192 * 193 * 0 4 8 12 16 20 24 28 194 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 195 * 196 * For OR3, need: 197 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 198 * disable buffer ctrl OR[19] = 0 199 * CSNT OR[20] = 1 200 * ACS OR[21:22] = 11 201 * XACS OR[23] = 1 202 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 203 * SETA OR[28] = 0 204 * TRLX OR[29] = 1 205 * EHTR OR[30] = 1 206 * EAD extra time OR[31] = 1 207 * 208 * 0 4 8 12 16 20 24 28 209 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 210 */ 211 212 #define CONFIG_FSL_CADMUS 213 214 #define CADMUS_BASE_ADDR 0xf8000000 215 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 216 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 217 218 #define CONFIG_SYS_INIT_RAM_LOCK 1 219 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 220 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 221 222 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 223 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 224 225 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 226 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 227 228 /* Serial Port */ 229 #define CONFIG_SYS_NS16550_SERIAL 230 #define CONFIG_SYS_NS16550_REG_SIZE 1 231 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 232 233 #define CONFIG_SYS_BAUDRATE_TABLE \ 234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 235 236 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 237 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 238 239 /* 240 * I2C 241 */ 242 #define CONFIG_SYS_I2C 243 #define CONFIG_SYS_I2C_FSL 244 #define CONFIG_SYS_FSL_I2C_SPEED 400000 245 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 246 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 247 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 248 249 /* EEPROM */ 250 #define CONFIG_ID_EEPROM 251 #define CONFIG_SYS_I2C_EEPROM_CCID 252 #define CONFIG_SYS_ID_EEPROM 253 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 254 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 255 256 /* 257 * General PCI 258 * Addresses are mapped 1-1. 259 */ 260 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 261 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 262 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 263 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 264 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 265 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 266 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 267 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 268 269 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 270 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 271 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 272 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 273 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 274 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 275 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 276 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 277 278 #ifdef CONFIG_LEGACY 279 #define BRIDGE_ID 17 280 #define VIA_ID 2 281 #else 282 #define BRIDGE_ID 28 283 #define VIA_ID 4 284 #endif 285 286 #if defined(CONFIG_PCI) 287 288 #define CONFIG_MPC85XX_PCI2 289 290 #undef CONFIG_EEPRO100 291 #undef CONFIG_TULIP 292 293 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 294 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 295 296 #endif /* CONFIG_PCI */ 297 298 #if defined(CONFIG_TSEC_ENET) 299 300 #define CONFIG_MII 1 /* MII PHY management */ 301 #define CONFIG_TSEC1 1 302 #define CONFIG_TSEC1_NAME "TSEC0" 303 #define CONFIG_TSEC2 1 304 #define CONFIG_TSEC2_NAME "TSEC1" 305 #define TSEC1_PHY_ADDR 0 306 #define TSEC2_PHY_ADDR 1 307 #define TSEC1_PHYIDX 0 308 #define TSEC2_PHYIDX 0 309 #define TSEC1_FLAGS TSEC_GIGABIT 310 #define TSEC2_FLAGS TSEC_GIGABIT 311 312 /* Options are: TSEC[0-1] */ 313 #define CONFIG_ETHPRIME "TSEC0" 314 315 #endif /* CONFIG_TSEC_ENET */ 316 317 /* 318 * Environment 319 */ 320 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 321 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 322 #define CONFIG_ENV_SIZE 0x2000 323 324 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 325 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 326 327 /* 328 * BOOTP options 329 */ 330 #define CONFIG_BOOTP_BOOTFILESIZE 331 332 #undef CONFIG_WATCHDOG /* watchdog disabled */ 333 334 /* 335 * Miscellaneous configurable options 336 */ 337 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 338 339 /* 340 * For booting Linux, the board info and command line data 341 * have to be in the first 64 MB of memory, since this is 342 * the maximum mapped by the Linux kernel during initialization. 343 */ 344 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 345 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 346 347 #if defined(CONFIG_CMD_KGDB) 348 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 349 #endif 350 351 /* 352 * Environment Configuration 353 */ 354 #if defined(CONFIG_TSEC_ENET) 355 #define CONFIG_HAS_ETH0 356 #define CONFIG_HAS_ETH1 357 #define CONFIG_HAS_ETH2 358 #endif 359 360 #define CONFIG_IPADDR 192.168.1.253 361 362 #define CONFIG_HOSTNAME "unknown" 363 #define CONFIG_ROOTPATH "/nfsroot" 364 #define CONFIG_BOOTFILE "your.uImage" 365 366 #define CONFIG_SERVERIP 192.168.1.1 367 #define CONFIG_GATEWAYIP 192.168.1.1 368 #define CONFIG_NETMASK 255.255.255.0 369 370 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 371 372 #define CONFIG_EXTRA_ENV_SETTINGS \ 373 "netdev=eth0\0" \ 374 "consoledev=ttyS1\0" \ 375 "ramdiskaddr=600000\0" \ 376 "ramdiskfile=your.ramdisk.u-boot\0" \ 377 "fdtaddr=400000\0" \ 378 "fdtfile=your.fdt.dtb\0" 379 380 #define CONFIG_NFSBOOTCOMMAND \ 381 "setenv bootargs root=/dev/nfs rw " \ 382 "nfsroot=$serverip:$rootpath " \ 383 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 384 "console=$consoledev,$baudrate $othbootargs;" \ 385 "tftp $loadaddr $bootfile;" \ 386 "tftp $fdtaddr $fdtfile;" \ 387 "bootm $loadaddr - $fdtaddr" 388 389 #define CONFIG_RAMBOOTCOMMAND \ 390 "setenv bootargs root=/dev/ram rw " \ 391 "console=$consoledev,$baudrate $othbootargs;" \ 392 "tftp $ramdiskaddr $ramdiskfile;" \ 393 "tftp $loadaddr $bootfile;" \ 394 "bootm $loadaddr $ramdiskaddr" 395 396 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 397 398 #endif /* __CONFIG_H */ 399