1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8555cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* High Level Configuration Options */ 16 #define CONFIG_CPM2 1 /* has CPM2 */ 17 18 #define CONFIG_PCI_INDIRECT_BRIDGE 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 #define CONFIG_ENV_OVERWRITE 21 22 #define CONFIG_FSL_VIA 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_clock_freq(void); 26 #endif 27 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 28 29 /* 30 * These can be toggled for performance analysis, otherwise use default. 31 */ 32 #define CONFIG_L2_CACHE /* toggle L2 cache */ 33 #define CONFIG_BTB /* toggle branch predition */ 34 35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 36 #define CONFIG_SYS_MEMTEST_END 0x00400000 37 38 #define CONFIG_SYS_CCSRBAR 0xe0000000 39 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 40 41 /* DDR Setup */ 42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 43 #define CONFIG_DDR_SPD 44 #undef CONFIG_FSL_DDR_INTERACTIVE 45 46 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 47 48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 50 51 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 52 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 53 54 /* I2C addresses of SPD EEPROMs */ 55 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 56 57 /* Make sure required options are set */ 58 #ifndef CONFIG_SPD_EEPROM 59 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 60 #endif 61 62 #undef CONFIG_CLOCKS_IN_MHZ 63 64 /* 65 * Local Bus Definitions 66 */ 67 68 /* 69 * FLASH on the Local Bus 70 * Two banks, 8M each, using the CFI driver. 71 * Boot from BR0/OR0 bank at 0xff00_0000 72 * Alternate BR1/OR1 bank at 0xff80_0000 73 * 74 * BR0, BR1: 75 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 76 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 77 * Port Size = 16 bits = BRx[19:20] = 10 78 * Use GPCM = BRx[24:26] = 000 79 * Valid = BRx[31] = 1 80 * 81 * 0 4 8 12 16 20 24 28 82 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 83 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 84 * 85 * OR0, OR1: 86 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 87 * Reserved ORx[17:18] = 11, confusion here? 88 * CSNT = ORx[20] = 1 89 * ACS = half cycle delay = ORx[21:22] = 11 90 * SCY = 6 = ORx[24:27] = 0110 91 * TRLX = use relaxed timing = ORx[29] = 1 92 * EAD = use external address latch delay = OR[31] = 1 93 * 94 * 0 4 8 12 16 20 24 28 95 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 96 */ 97 98 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 99 100 #define CONFIG_SYS_BR0_PRELIM 0xff801001 101 #define CONFIG_SYS_BR1_PRELIM 0xff001001 102 103 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 104 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 105 106 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 107 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 108 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 109 #undef CONFIG_SYS_FLASH_CHECKSUM 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 114 115 #define CONFIG_FLASH_CFI_DRIVER 116 #define CONFIG_SYS_FLASH_CFI 117 #define CONFIG_SYS_FLASH_EMPTY_INFO 118 119 /* 120 * SDRAM on the Local Bus 121 */ 122 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 123 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 124 125 /* 126 * Base Register 2 and Option Register 2 configure SDRAM. 127 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 128 * 129 * For BR2, need: 130 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 131 * port-size = 32-bits = BR2[19:20] = 11 132 * no parity checking = BR2[21:22] = 00 133 * SDRAM for MSEL = BR2[24:26] = 011 134 * Valid = BR[31] = 1 135 * 136 * 0 4 8 12 16 20 24 28 137 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 138 * 139 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 140 * FIXME: the top 17 bits of BR2. 141 */ 142 143 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 144 145 /* 146 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 147 * 148 * For OR2, need: 149 * 64MB mask for AM, OR2[0:7] = 1111 1100 150 * XAM, OR2[17:18] = 11 151 * 9 columns OR2[19-21] = 010 152 * 13 rows OR2[23-25] = 100 153 * EAD set for extra time OR[31] = 1 154 * 155 * 0 4 8 12 16 20 24 28 156 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 157 */ 158 159 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 160 161 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 162 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 163 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 164 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 165 166 /* 167 * Common settings for all Local Bus SDRAM commands. 168 * At run time, either BSMA1516 (for CPU 1.1) 169 * or BSMA1617 (for CPU 1.0) (old) 170 * is OR'ed in too. 171 */ 172 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 173 | LSDMR_PRETOACT7 \ 174 | LSDMR_ACTTORW7 \ 175 | LSDMR_BL8 \ 176 | LSDMR_WRC4 \ 177 | LSDMR_CL3 \ 178 | LSDMR_RFEN \ 179 ) 180 181 /* 182 * The CADMUS registers are connected to CS3 on CDS. 183 * The new memory map places CADMUS at 0xf8000000. 184 * 185 * For BR3, need: 186 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 187 * port-size = 8-bits = BR[19:20] = 01 188 * no parity checking = BR[21:22] = 00 189 * GPMC for MSEL = BR[24:26] = 000 190 * Valid = BR[31] = 1 191 * 192 * 0 4 8 12 16 20 24 28 193 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 194 * 195 * For OR3, need: 196 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 197 * disable buffer ctrl OR[19] = 0 198 * CSNT OR[20] = 1 199 * ACS OR[21:22] = 11 200 * XACS OR[23] = 1 201 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 202 * SETA OR[28] = 0 203 * TRLX OR[29] = 1 204 * EHTR OR[30] = 1 205 * EAD extra time OR[31] = 1 206 * 207 * 0 4 8 12 16 20 24 28 208 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 209 */ 210 211 #define CONFIG_FSL_CADMUS 212 213 #define CADMUS_BASE_ADDR 0xf8000000 214 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 215 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 216 217 #define CONFIG_SYS_INIT_RAM_LOCK 1 218 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 219 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 220 221 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 222 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 223 224 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 225 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 226 227 /* Serial Port */ 228 #define CONFIG_SYS_NS16550_SERIAL 229 #define CONFIG_SYS_NS16550_REG_SIZE 1 230 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 231 232 #define CONFIG_SYS_BAUDRATE_TABLE \ 233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 234 235 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 236 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 237 238 /* 239 * I2C 240 */ 241 #define CONFIG_SYS_I2C 242 #define CONFIG_SYS_I2C_FSL 243 #define CONFIG_SYS_FSL_I2C_SPEED 400000 244 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 245 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 246 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 247 248 /* EEPROM */ 249 #define CONFIG_ID_EEPROM 250 #define CONFIG_SYS_I2C_EEPROM_CCID 251 #define CONFIG_SYS_ID_EEPROM 252 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 253 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 254 255 /* 256 * General PCI 257 * Addresses are mapped 1-1. 258 */ 259 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 261 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 262 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 263 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 264 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 265 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 266 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 267 268 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 269 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 270 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 271 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 272 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 273 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 274 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 275 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 276 277 #ifdef CONFIG_LEGACY 278 #define BRIDGE_ID 17 279 #define VIA_ID 2 280 #else 281 #define BRIDGE_ID 28 282 #define VIA_ID 4 283 #endif 284 285 #if defined(CONFIG_PCI) 286 287 #define CONFIG_MPC85XX_PCI2 288 289 #undef CONFIG_EEPRO100 290 #undef CONFIG_TULIP 291 292 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 293 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 294 295 #endif /* CONFIG_PCI */ 296 297 #if defined(CONFIG_TSEC_ENET) 298 299 #define CONFIG_MII 1 /* MII PHY management */ 300 #define CONFIG_TSEC1 1 301 #define CONFIG_TSEC1_NAME "TSEC0" 302 #define CONFIG_TSEC2 1 303 #define CONFIG_TSEC2_NAME "TSEC1" 304 #define TSEC1_PHY_ADDR 0 305 #define TSEC2_PHY_ADDR 1 306 #define TSEC1_PHYIDX 0 307 #define TSEC2_PHYIDX 0 308 #define TSEC1_FLAGS TSEC_GIGABIT 309 #define TSEC2_FLAGS TSEC_GIGABIT 310 311 /* Options are: TSEC[0-1] */ 312 #define CONFIG_ETHPRIME "TSEC0" 313 314 #endif /* CONFIG_TSEC_ENET */ 315 316 /* 317 * Environment 318 */ 319 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 320 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 321 #define CONFIG_ENV_SIZE 0x2000 322 323 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 324 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 325 326 /* 327 * BOOTP options 328 */ 329 #define CONFIG_BOOTP_BOOTFILESIZE 330 331 #undef CONFIG_WATCHDOG /* watchdog disabled */ 332 333 /* 334 * Miscellaneous configurable options 335 */ 336 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 337 338 /* 339 * For booting Linux, the board info and command line data 340 * have to be in the first 64 MB of memory, since this is 341 * the maximum mapped by the Linux kernel during initialization. 342 */ 343 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 344 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 345 346 #if defined(CONFIG_CMD_KGDB) 347 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 348 #endif 349 350 /* 351 * Environment Configuration 352 */ 353 #if defined(CONFIG_TSEC_ENET) 354 #define CONFIG_HAS_ETH0 355 #define CONFIG_HAS_ETH1 356 #define CONFIG_HAS_ETH2 357 #endif 358 359 #define CONFIG_IPADDR 192.168.1.253 360 361 #define CONFIG_HOSTNAME "unknown" 362 #define CONFIG_ROOTPATH "/nfsroot" 363 #define CONFIG_BOOTFILE "your.uImage" 364 365 #define CONFIG_SERVERIP 192.168.1.1 366 #define CONFIG_GATEWAYIP 192.168.1.1 367 #define CONFIG_NETMASK 255.255.255.0 368 369 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 370 371 #define CONFIG_EXTRA_ENV_SETTINGS \ 372 "netdev=eth0\0" \ 373 "consoledev=ttyS1\0" \ 374 "ramdiskaddr=600000\0" \ 375 "ramdiskfile=your.ramdisk.u-boot\0" \ 376 "fdtaddr=400000\0" \ 377 "fdtfile=your.fdt.dtb\0" 378 379 #define CONFIG_NFSBOOTCOMMAND \ 380 "setenv bootargs root=/dev/nfs rw " \ 381 "nfsroot=$serverip:$rootpath " \ 382 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 383 "console=$consoledev,$baudrate $othbootargs;" \ 384 "tftp $loadaddr $bootfile;" \ 385 "tftp $fdtaddr $fdtfile;" \ 386 "bootm $loadaddr - $fdtaddr" 387 388 #define CONFIG_RAMBOOTCOMMAND \ 389 "setenv bootargs root=/dev/ram rw " \ 390 "console=$consoledev,$baudrate $othbootargs;" \ 391 "tftp $ramdiskaddr $ramdiskfile;" \ 392 "tftp $loadaddr $bootfile;" \ 393 "bootm $loadaddr $ramdiskaddr" 394 395 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 396 397 #endif /* __CONFIG_H */ 398