1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8555cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 36 #define CONFIG_CPM2 1 /* has CPM2 */ 37 #define CONFIG_MPC8555 1 /* MPC8555 specific */ 38 #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ 39 40 #define CONFIG_PCI 41 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 44 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 45 #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 46 47 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 48 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 49 50 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 51 52 #define CONFIG_FSL_VIA 53 #define CONFIG_FSL_CDS_EEPROM 54 55 /* 56 * When initializing flash, if we cannot find the manufacturer ID, 57 * assume this is the AMD flash associated with the CDS board. 58 * This allows booting from a promjet. 59 */ 60 #define CONFIG_ASSUME_AMD_FLASH 61 62 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 63 64 #ifndef __ASSEMBLY__ 65 extern unsigned long get_clock_freq(void); 66 #endif 67 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 73 #define CONFIG_BTB /* toggle branch predition */ 74 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 75 76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 77 78 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 79 #define CFG_MEMTEST_END 0x00400000 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 87 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 88 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 89 90 /* 91 * DDR Setup 92 */ 93 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 94 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 95 96 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 97 98 /* 99 * Make sure required options are set 100 */ 101 #ifndef CONFIG_SPD_EEPROM 102 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 103 #endif 104 105 #undef CONFIG_CLOCKS_IN_MHZ 106 107 108 /* 109 * Local Bus Definitions 110 */ 111 112 /* 113 * FLASH on the Local Bus 114 * Two banks, 8M each, using the CFI driver. 115 * Boot from BR0/OR0 bank at 0xff00_0000 116 * Alternate BR1/OR1 bank at 0xff80_0000 117 * 118 * BR0, BR1: 119 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 120 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 121 * Port Size = 16 bits = BRx[19:20] = 10 122 * Use GPCM = BRx[24:26] = 000 123 * Valid = BRx[31] = 1 124 * 125 * 0 4 8 12 16 20 24 28 126 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 127 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 128 * 129 * OR0, OR1: 130 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 131 * Reserved ORx[17:18] = 11, confusion here? 132 * CSNT = ORx[20] = 1 133 * ACS = half cycle delay = ORx[21:22] = 11 134 * SCY = 6 = ORx[24:27] = 0110 135 * TRLX = use relaxed timing = ORx[29] = 1 136 * EAD = use external address latch delay = OR[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 140 */ 141 142 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 143 144 #define CFG_BR0_PRELIM 0xff801001 145 #define CFG_BR1_PRELIM 0xff001001 146 147 #define CFG_OR0_PRELIM 0xff806e65 148 #define CFG_OR1_PRELIM 0xff806e65 149 150 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 151 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 152 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 153 #undef CFG_FLASH_CHECKSUM 154 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 155 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 156 157 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 158 159 #define CFG_FLASH_CFI_DRIVER 160 #define CFG_FLASH_CFI 161 #define CFG_FLASH_EMPTY_INFO 162 163 164 /* 165 * SDRAM on the Local Bus 166 */ 167 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 168 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 169 170 /* 171 * Base Register 2 and Option Register 2 configure SDRAM. 172 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 173 * 174 * For BR2, need: 175 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 176 * port-size = 32-bits = BR2[19:20] = 11 177 * no parity checking = BR2[21:22] = 00 178 * SDRAM for MSEL = BR2[24:26] = 011 179 * Valid = BR[31] = 1 180 * 181 * 0 4 8 12 16 20 24 28 182 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 183 * 184 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 185 * FIXME: the top 17 bits of BR2. 186 */ 187 188 #define CFG_BR2_PRELIM 0xf0001861 189 190 /* 191 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 192 * 193 * For OR2, need: 194 * 64MB mask for AM, OR2[0:7] = 1111 1100 195 * XAM, OR2[17:18] = 11 196 * 9 columns OR2[19-21] = 010 197 * 13 rows OR2[23-25] = 100 198 * EAD set for extra time OR[31] = 1 199 * 200 * 0 4 8 12 16 20 24 28 201 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 202 */ 203 204 #define CFG_OR2_PRELIM 0xfc006901 205 206 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 207 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 208 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 209 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 210 211 /* 212 * LSDMR masks 213 */ 214 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 215 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 216 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 217 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 218 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 219 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 220 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 221 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 222 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 223 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 224 225 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 226 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 227 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 228 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 229 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 230 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 231 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 232 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 233 234 /* 235 * Common settings for all Local Bus SDRAM commands. 236 * At run time, either BSMA1516 (for CPU 1.1) 237 * or BSMA1617 (for CPU 1.0) (old) 238 * is OR'ed in too. 239 */ 240 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 241 | CFG_LBC_LSDMR_PRETOACT7 \ 242 | CFG_LBC_LSDMR_ACTTORW7 \ 243 | CFG_LBC_LSDMR_BL8 \ 244 | CFG_LBC_LSDMR_WRC4 \ 245 | CFG_LBC_LSDMR_CL3 \ 246 | CFG_LBC_LSDMR_RFEN \ 247 ) 248 249 /* 250 * The CADMUS registers are connected to CS3 on CDS. 251 * The new memory map places CADMUS at 0xf8000000. 252 * 253 * For BR3, need: 254 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 255 * port-size = 8-bits = BR[19:20] = 01 256 * no parity checking = BR[21:22] = 00 257 * GPMC for MSEL = BR[24:26] = 000 258 * Valid = BR[31] = 1 259 * 260 * 0 4 8 12 16 20 24 28 261 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 262 * 263 * For OR3, need: 264 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 265 * disable buffer ctrl OR[19] = 0 266 * CSNT OR[20] = 1 267 * ACS OR[21:22] = 11 268 * XACS OR[23] = 1 269 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 270 * SETA OR[28] = 0 271 * TRLX OR[29] = 1 272 * EHTR OR[30] = 1 273 * EAD extra time OR[31] = 1 274 * 275 * 0 4 8 12 16 20 24 28 276 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 277 */ 278 279 #define CONFIG_FSL_CADMUS 280 281 #define CADMUS_BASE_ADDR 0xf8000000 282 #define CFG_BR3_PRELIM 0xf8000801 283 #define CFG_OR3_PRELIM 0xfff00ff7 284 285 #define CONFIG_L1_INIT_RAM 286 #define CFG_INIT_RAM_LOCK 1 287 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 288 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 289 290 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 291 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 292 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 293 294 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 295 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 296 297 /* Serial Port */ 298 #define CONFIG_CONS_INDEX 2 299 #undef CONFIG_SERIAL_SOFTWARE_FIFO 300 #define CFG_NS16550 301 #define CFG_NS16550_SERIAL 302 #define CFG_NS16550_REG_SIZE 1 303 #define CFG_NS16550_CLK get_bus_freq(0) 304 305 #define CFG_BAUDRATE_TABLE \ 306 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 307 308 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 309 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 310 311 /* Use the HUSH parser */ 312 #define CFG_HUSH_PARSER 313 #ifdef CFG_HUSH_PARSER 314 #define CFG_PROMPT_HUSH_PS2 "> " 315 #endif 316 317 /* pass open firmware flat tree */ 318 #define CONFIG_OF_LIBFDT 1 319 #define CONFIG_OF_BOARD_SETUP 1 320 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 321 322 /* 323 * I2C 324 */ 325 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 326 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 327 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 328 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 329 #define CFG_I2C_EEPROM_ADDR 0x57 330 #define CFG_I2C_SLAVE 0x7F 331 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 332 #define CFG_I2C_OFFSET 0x3000 333 334 /* 335 * General PCI 336 * Addresses are mapped 1-1. 337 */ 338 #define CFG_PCI1_MEM_BASE 0x80000000 339 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 340 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 341 #define CFG_PCI1_IO_BASE 0x00000000 342 #define CFG_PCI1_IO_PHYS 0xe2000000 343 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 344 345 #define CFG_PCI2_MEM_BASE 0xa0000000 346 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 347 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 348 #define CFG_PCI2_IO_BASE 0x00000000 349 #define CFG_PCI2_IO_PHYS 0xe2100000 350 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 351 352 #ifdef CONFIG_LEGACY 353 #define BRIDGE_ID 17 354 #define VIA_ID 2 355 #else 356 #define BRIDGE_ID 28 357 #define VIA_ID 4 358 #endif 359 360 #if defined(CONFIG_PCI) 361 362 #define CONFIG_NET_MULTI 363 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 364 #define CONFIG_MPC85XX_PCI2 365 366 #undef CONFIG_EEPRO100 367 #undef CONFIG_TULIP 368 369 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 370 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 371 372 #endif /* CONFIG_PCI */ 373 374 375 #if defined(CONFIG_TSEC_ENET) 376 377 #ifndef CONFIG_NET_MULTI 378 #define CONFIG_NET_MULTI 1 379 #endif 380 381 #define CONFIG_MII 1 /* MII PHY management */ 382 #define CONFIG_TSEC1 1 383 #define CONFIG_TSEC1_NAME "TSEC0" 384 #define CONFIG_TSEC2 1 385 #define CONFIG_TSEC2_NAME "TSEC1" 386 #define TSEC1_PHY_ADDR 0 387 #define TSEC2_PHY_ADDR 1 388 #define TSEC1_PHYIDX 0 389 #define TSEC2_PHYIDX 0 390 #define TSEC1_FLAGS TSEC_GIGABIT 391 #define TSEC2_FLAGS TSEC_GIGABIT 392 393 /* Options are: TSEC[0-1] */ 394 #define CONFIG_ETHPRIME "TSEC0" 395 396 #endif /* CONFIG_TSEC_ENET */ 397 398 /* 399 * Environment 400 */ 401 #define CFG_ENV_IS_IN_FLASH 1 402 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 403 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 404 #define CFG_ENV_SIZE 0x2000 405 406 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 407 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 408 409 /* 410 * BOOTP options 411 */ 412 #define CONFIG_BOOTP_BOOTFILESIZE 413 #define CONFIG_BOOTP_BOOTPATH 414 #define CONFIG_BOOTP_GATEWAY 415 #define CONFIG_BOOTP_HOSTNAME 416 417 418 /* 419 * Command line configuration. 420 */ 421 #include <config_cmd_default.h> 422 423 #define CONFIG_CMD_PING 424 #define CONFIG_CMD_I2C 425 #define CONFIG_CMD_MII 426 #define CONFIG_CMD_ELF 427 428 #if defined(CONFIG_PCI) 429 #define CONFIG_CMD_PCI 430 #endif 431 432 433 #undef CONFIG_WATCHDOG /* watchdog disabled */ 434 435 /* 436 * Miscellaneous configurable options 437 */ 438 #define CFG_LONGHELP /* undef to save memory */ 439 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 440 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 441 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 442 #if defined(CONFIG_CMD_KGDB) 443 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 444 #else 445 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 446 #endif 447 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 448 #define CFG_MAXARGS 16 /* max number of command args */ 449 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 450 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 451 452 /* 453 * For booting Linux, the board info and command line data 454 * have to be in the first 8 MB of memory, since this is 455 * the maximum mapped by the Linux kernel during initialization. 456 */ 457 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 458 459 /* 460 * Internal Definitions 461 * 462 * Boot Flags 463 */ 464 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 465 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 466 467 #if defined(CONFIG_CMD_KGDB) 468 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 469 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 470 #endif 471 472 /* 473 * Environment Configuration 474 */ 475 476 /* The mac addresses for all ethernet interface */ 477 #if defined(CONFIG_TSEC_ENET) 478 #define CONFIG_HAS_ETH0 479 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 480 #define CONFIG_HAS_ETH1 481 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 482 #define CONFIG_HAS_ETH2 483 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 484 #endif 485 486 #define CONFIG_IPADDR 192.168.1.253 487 488 #define CONFIG_HOSTNAME unknown 489 #define CONFIG_ROOTPATH /nfsroot 490 #define CONFIG_BOOTFILE your.uImage 491 492 #define CONFIG_SERVERIP 192.168.1.1 493 #define CONFIG_GATEWAYIP 192.168.1.1 494 #define CONFIG_NETMASK 255.255.255.0 495 496 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 497 498 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 499 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 500 501 #define CONFIG_BAUDRATE 115200 502 503 #define CONFIG_EXTRA_ENV_SETTINGS \ 504 "netdev=eth0\0" \ 505 "consoledev=ttyS1\0" \ 506 "ramdiskaddr=600000\0" \ 507 "ramdiskfile=your.ramdisk.u-boot\0" \ 508 "fdtaddr=400000\0" \ 509 "fdtfile=your.fdt.dtb\0" 510 511 #define CONFIG_NFSBOOTCOMMAND \ 512 "setenv bootargs root=/dev/nfs rw " \ 513 "nfsroot=$serverip:$rootpath " \ 514 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 515 "console=$consoledev,$baudrate $othbootargs;" \ 516 "tftp $loadaddr $bootfile;" \ 517 "tftp $fdtaddr $fdtfile;" \ 518 "bootm $loadaddr - $fdtaddr" 519 520 #define CONFIG_RAMBOOTCOMMAND \ 521 "setenv bootargs root=/dev/ram rw " \ 522 "console=$consoledev,$baudrate $othbootargs;" \ 523 "tftp $ramdiskaddr $ramdiskfile;" \ 524 "tftp $loadaddr $bootfile;" \ 525 "bootm $loadaddr $ramdiskaddr" 526 527 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 528 529 #endif /* __CONFIG_H */ 530