1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8555cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_CPM2 1 /* has CPM2 */ 18 19 #define CONFIG_SYS_TEXT_BASE 0xfff80000 20 21 #define CONFIG_PCI_INDIRECT_BRIDGE 22 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 23 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 24 #define CONFIG_ENV_OVERWRITE 25 26 #define CONFIG_FSL_VIA 27 28 #ifndef __ASSEMBLY__ 29 extern unsigned long get_clock_freq(void); 30 #endif 31 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 32 33 /* 34 * These can be toggled for performance analysis, otherwise use default. 35 */ 36 #define CONFIG_L2_CACHE /* toggle L2 cache */ 37 #define CONFIG_BTB /* toggle branch predition */ 38 39 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 40 #define CONFIG_SYS_MEMTEST_END 0x00400000 41 42 #define CONFIG_SYS_CCSRBAR 0xe0000000 43 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 44 45 /* DDR Setup */ 46 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 47 #define CONFIG_DDR_SPD 48 #undef CONFIG_FSL_DDR_INTERACTIVE 49 50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 51 52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 53 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 54 55 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 56 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 57 58 /* I2C addresses of SPD EEPROMs */ 59 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 60 61 /* Make sure required options are set */ 62 #ifndef CONFIG_SPD_EEPROM 63 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 64 #endif 65 66 #undef CONFIG_CLOCKS_IN_MHZ 67 68 /* 69 * Local Bus Definitions 70 */ 71 72 /* 73 * FLASH on the Local Bus 74 * Two banks, 8M each, using the CFI driver. 75 * Boot from BR0/OR0 bank at 0xff00_0000 76 * Alternate BR1/OR1 bank at 0xff80_0000 77 * 78 * BR0, BR1: 79 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 80 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 81 * Port Size = 16 bits = BRx[19:20] = 10 82 * Use GPCM = BRx[24:26] = 000 83 * Valid = BRx[31] = 1 84 * 85 * 0 4 8 12 16 20 24 28 86 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 87 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 88 * 89 * OR0, OR1: 90 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 91 * Reserved ORx[17:18] = 11, confusion here? 92 * CSNT = ORx[20] = 1 93 * ACS = half cycle delay = ORx[21:22] = 11 94 * SCY = 6 = ORx[24:27] = 0110 95 * TRLX = use relaxed timing = ORx[29] = 1 96 * EAD = use external address latch delay = OR[31] = 1 97 * 98 * 0 4 8 12 16 20 24 28 99 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 100 */ 101 102 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 103 104 #define CONFIG_SYS_BR0_PRELIM 0xff801001 105 #define CONFIG_SYS_BR1_PRELIM 0xff001001 106 107 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 108 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 109 110 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 111 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 112 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 113 #undef CONFIG_SYS_FLASH_CHECKSUM 114 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 115 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 116 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 118 119 #define CONFIG_FLASH_CFI_DRIVER 120 #define CONFIG_SYS_FLASH_CFI 121 #define CONFIG_SYS_FLASH_EMPTY_INFO 122 123 /* 124 * SDRAM on the Local Bus 125 */ 126 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 127 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 128 129 /* 130 * Base Register 2 and Option Register 2 configure SDRAM. 131 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 132 * 133 * For BR2, need: 134 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 135 * port-size = 32-bits = BR2[19:20] = 11 136 * no parity checking = BR2[21:22] = 00 137 * SDRAM for MSEL = BR2[24:26] = 011 138 * Valid = BR[31] = 1 139 * 140 * 0 4 8 12 16 20 24 28 141 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 142 * 143 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 144 * FIXME: the top 17 bits of BR2. 145 */ 146 147 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 148 149 /* 150 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 151 * 152 * For OR2, need: 153 * 64MB mask for AM, OR2[0:7] = 1111 1100 154 * XAM, OR2[17:18] = 11 155 * 9 columns OR2[19-21] = 010 156 * 13 rows OR2[23-25] = 100 157 * EAD set for extra time OR[31] = 1 158 * 159 * 0 4 8 12 16 20 24 28 160 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 161 */ 162 163 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 164 165 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 166 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 167 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 168 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 169 170 /* 171 * Common settings for all Local Bus SDRAM commands. 172 * At run time, either BSMA1516 (for CPU 1.1) 173 * or BSMA1617 (for CPU 1.0) (old) 174 * is OR'ed in too. 175 */ 176 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 177 | LSDMR_PRETOACT7 \ 178 | LSDMR_ACTTORW7 \ 179 | LSDMR_BL8 \ 180 | LSDMR_WRC4 \ 181 | LSDMR_CL3 \ 182 | LSDMR_RFEN \ 183 ) 184 185 /* 186 * The CADMUS registers are connected to CS3 on CDS. 187 * The new memory map places CADMUS at 0xf8000000. 188 * 189 * For BR3, need: 190 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 191 * port-size = 8-bits = BR[19:20] = 01 192 * no parity checking = BR[21:22] = 00 193 * GPMC for MSEL = BR[24:26] = 000 194 * Valid = BR[31] = 1 195 * 196 * 0 4 8 12 16 20 24 28 197 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 198 * 199 * For OR3, need: 200 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 201 * disable buffer ctrl OR[19] = 0 202 * CSNT OR[20] = 1 203 * ACS OR[21:22] = 11 204 * XACS OR[23] = 1 205 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 206 * SETA OR[28] = 0 207 * TRLX OR[29] = 1 208 * EHTR OR[30] = 1 209 * EAD extra time OR[31] = 1 210 * 211 * 0 4 8 12 16 20 24 28 212 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 213 */ 214 215 #define CONFIG_FSL_CADMUS 216 217 #define CADMUS_BASE_ADDR 0xf8000000 218 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 219 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 220 221 #define CONFIG_SYS_INIT_RAM_LOCK 1 222 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 223 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 224 225 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 227 228 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 229 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 230 231 /* Serial Port */ 232 #define CONFIG_CONS_INDEX 2 233 #define CONFIG_SYS_NS16550_SERIAL 234 #define CONFIG_SYS_NS16550_REG_SIZE 1 235 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 236 237 #define CONFIG_SYS_BAUDRATE_TABLE \ 238 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 239 240 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 241 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 242 243 /* 244 * I2C 245 */ 246 #define CONFIG_SYS_I2C 247 #define CONFIG_SYS_I2C_FSL 248 #define CONFIG_SYS_FSL_I2C_SPEED 400000 249 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 250 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 251 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 252 253 /* EEPROM */ 254 #define CONFIG_ID_EEPROM 255 #define CONFIG_SYS_I2C_EEPROM_CCID 256 #define CONFIG_SYS_ID_EEPROM 257 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 258 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 259 260 /* 261 * General PCI 262 * Addresses are mapped 1-1. 263 */ 264 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 265 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 266 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 267 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 268 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 269 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 270 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 271 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 272 273 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 274 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 275 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 276 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 277 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 278 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 279 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 280 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 281 282 #ifdef CONFIG_LEGACY 283 #define BRIDGE_ID 17 284 #define VIA_ID 2 285 #else 286 #define BRIDGE_ID 28 287 #define VIA_ID 4 288 #endif 289 290 #if defined(CONFIG_PCI) 291 292 #define CONFIG_MPC85XX_PCI2 293 294 #undef CONFIG_EEPRO100 295 #undef CONFIG_TULIP 296 297 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 298 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 299 300 #endif /* CONFIG_PCI */ 301 302 #if defined(CONFIG_TSEC_ENET) 303 304 #define CONFIG_MII 1 /* MII PHY management */ 305 #define CONFIG_TSEC1 1 306 #define CONFIG_TSEC1_NAME "TSEC0" 307 #define CONFIG_TSEC2 1 308 #define CONFIG_TSEC2_NAME "TSEC1" 309 #define TSEC1_PHY_ADDR 0 310 #define TSEC2_PHY_ADDR 1 311 #define TSEC1_PHYIDX 0 312 #define TSEC2_PHYIDX 0 313 #define TSEC1_FLAGS TSEC_GIGABIT 314 #define TSEC2_FLAGS TSEC_GIGABIT 315 316 /* Options are: TSEC[0-1] */ 317 #define CONFIG_ETHPRIME "TSEC0" 318 319 #endif /* CONFIG_TSEC_ENET */ 320 321 /* 322 * Environment 323 */ 324 #define CONFIG_ENV_IS_IN_FLASH 1 325 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 326 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 327 #define CONFIG_ENV_SIZE 0x2000 328 329 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 330 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 331 332 /* 333 * BOOTP options 334 */ 335 #define CONFIG_BOOTP_BOOTFILESIZE 336 #define CONFIG_BOOTP_BOOTPATH 337 #define CONFIG_BOOTP_GATEWAY 338 #define CONFIG_BOOTP_HOSTNAME 339 340 /* 341 * Command line configuration. 342 */ 343 #define CONFIG_CMD_IRQ 344 #define CONFIG_CMD_REGINFO 345 346 #if defined(CONFIG_PCI) 347 #define CONFIG_CMD_PCI 348 #endif 349 350 #undef CONFIG_WATCHDOG /* watchdog disabled */ 351 352 /* 353 * Miscellaneous configurable options 354 */ 355 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 356 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 357 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 358 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 359 #if defined(CONFIG_CMD_KGDB) 360 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 361 #else 362 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 363 #endif 364 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 365 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 366 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 367 368 /* 369 * For booting Linux, the board info and command line data 370 * have to be in the first 64 MB of memory, since this is 371 * the maximum mapped by the Linux kernel during initialization. 372 */ 373 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 374 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 375 376 #if defined(CONFIG_CMD_KGDB) 377 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 378 #endif 379 380 /* 381 * Environment Configuration 382 */ 383 #if defined(CONFIG_TSEC_ENET) 384 #define CONFIG_HAS_ETH0 385 #define CONFIG_HAS_ETH1 386 #define CONFIG_HAS_ETH2 387 #endif 388 389 #define CONFIG_IPADDR 192.168.1.253 390 391 #define CONFIG_HOSTNAME unknown 392 #define CONFIG_ROOTPATH "/nfsroot" 393 #define CONFIG_BOOTFILE "your.uImage" 394 395 #define CONFIG_SERVERIP 192.168.1.1 396 #define CONFIG_GATEWAYIP 192.168.1.1 397 #define CONFIG_NETMASK 255.255.255.0 398 399 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 400 401 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 402 403 #define CONFIG_BAUDRATE 115200 404 405 #define CONFIG_EXTRA_ENV_SETTINGS \ 406 "netdev=eth0\0" \ 407 "consoledev=ttyS1\0" \ 408 "ramdiskaddr=600000\0" \ 409 "ramdiskfile=your.ramdisk.u-boot\0" \ 410 "fdtaddr=400000\0" \ 411 "fdtfile=your.fdt.dtb\0" 412 413 #define CONFIG_NFSBOOTCOMMAND \ 414 "setenv bootargs root=/dev/nfs rw " \ 415 "nfsroot=$serverip:$rootpath " \ 416 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 417 "console=$consoledev,$baudrate $othbootargs;" \ 418 "tftp $loadaddr $bootfile;" \ 419 "tftp $fdtaddr $fdtfile;" \ 420 "bootm $loadaddr - $fdtaddr" 421 422 #define CONFIG_RAMBOOTCOMMAND \ 423 "setenv bootargs root=/dev/ram rw " \ 424 "console=$consoledev,$baudrate $othbootargs;" \ 425 "tftp $ramdiskaddr $ramdiskfile;" \ 426 "tftp $loadaddr $bootfile;" \ 427 "bootm $loadaddr $ramdiskaddr" 428 429 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 430 431 #endif /* __CONFIG_H */ 432