1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8555cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* High Level Configuration Options */ 16 #define CONFIG_CPM2 1 /* has CPM2 */ 17 18 #define CONFIG_PCI_INDIRECT_BRIDGE 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 #define CONFIG_ENV_OVERWRITE 21 22 #define CONFIG_FSL_VIA 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_clock_freq(void); 26 #endif 27 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 28 29 /* 30 * These can be toggled for performance analysis, otherwise use default. 31 */ 32 #define CONFIG_L2_CACHE /* toggle L2 cache */ 33 #define CONFIG_BTB /* toggle branch predition */ 34 35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 36 #define CONFIG_SYS_MEMTEST_END 0x00400000 37 38 #define CONFIG_SYS_CCSRBAR 0xe0000000 39 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 40 41 /* DDR Setup */ 42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 43 #define CONFIG_DDR_SPD 44 #undef CONFIG_FSL_DDR_INTERACTIVE 45 46 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 47 48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 50 51 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 52 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 53 54 /* I2C addresses of SPD EEPROMs */ 55 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 56 57 /* Make sure required options are set */ 58 #ifndef CONFIG_SPD_EEPROM 59 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 60 #endif 61 62 #undef CONFIG_CLOCKS_IN_MHZ 63 64 /* 65 * Local Bus Definitions 66 */ 67 68 /* 69 * FLASH on the Local Bus 70 * Two banks, 8M each, using the CFI driver. 71 * Boot from BR0/OR0 bank at 0xff00_0000 72 * Alternate BR1/OR1 bank at 0xff80_0000 73 * 74 * BR0, BR1: 75 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 76 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 77 * Port Size = 16 bits = BRx[19:20] = 10 78 * Use GPCM = BRx[24:26] = 000 79 * Valid = BRx[31] = 1 80 * 81 * 0 4 8 12 16 20 24 28 82 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 83 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 84 * 85 * OR0, OR1: 86 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 87 * Reserved ORx[17:18] = 11, confusion here? 88 * CSNT = ORx[20] = 1 89 * ACS = half cycle delay = ORx[21:22] = 11 90 * SCY = 6 = ORx[24:27] = 0110 91 * TRLX = use relaxed timing = ORx[29] = 1 92 * EAD = use external address latch delay = OR[31] = 1 93 * 94 * 0 4 8 12 16 20 24 28 95 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 96 */ 97 98 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 99 100 #define CONFIG_SYS_BR0_PRELIM 0xff801001 101 #define CONFIG_SYS_BR1_PRELIM 0xff001001 102 103 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 104 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 105 106 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 107 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 108 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 109 #undef CONFIG_SYS_FLASH_CHECKSUM 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 114 115 #define CONFIG_SYS_FLASH_EMPTY_INFO 116 117 /* 118 * SDRAM on the Local Bus 119 */ 120 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 121 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 122 123 /* 124 * Base Register 2 and Option Register 2 configure SDRAM. 125 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 126 * 127 * For BR2, need: 128 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 129 * port-size = 32-bits = BR2[19:20] = 11 130 * no parity checking = BR2[21:22] = 00 131 * SDRAM for MSEL = BR2[24:26] = 011 132 * Valid = BR[31] = 1 133 * 134 * 0 4 8 12 16 20 24 28 135 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 136 * 137 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 138 * FIXME: the top 17 bits of BR2. 139 */ 140 141 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 142 143 /* 144 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 145 * 146 * For OR2, need: 147 * 64MB mask for AM, OR2[0:7] = 1111 1100 148 * XAM, OR2[17:18] = 11 149 * 9 columns OR2[19-21] = 010 150 * 13 rows OR2[23-25] = 100 151 * EAD set for extra time OR[31] = 1 152 * 153 * 0 4 8 12 16 20 24 28 154 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 155 */ 156 157 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 158 159 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 160 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 161 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 162 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 163 164 /* 165 * Common settings for all Local Bus SDRAM commands. 166 * At run time, either BSMA1516 (for CPU 1.1) 167 * or BSMA1617 (for CPU 1.0) (old) 168 * is OR'ed in too. 169 */ 170 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 171 | LSDMR_PRETOACT7 \ 172 | LSDMR_ACTTORW7 \ 173 | LSDMR_BL8 \ 174 | LSDMR_WRC4 \ 175 | LSDMR_CL3 \ 176 | LSDMR_RFEN \ 177 ) 178 179 /* 180 * The CADMUS registers are connected to CS3 on CDS. 181 * The new memory map places CADMUS at 0xf8000000. 182 * 183 * For BR3, need: 184 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 185 * port-size = 8-bits = BR[19:20] = 01 186 * no parity checking = BR[21:22] = 00 187 * GPMC for MSEL = BR[24:26] = 000 188 * Valid = BR[31] = 1 189 * 190 * 0 4 8 12 16 20 24 28 191 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 192 * 193 * For OR3, need: 194 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 195 * disable buffer ctrl OR[19] = 0 196 * CSNT OR[20] = 1 197 * ACS OR[21:22] = 11 198 * XACS OR[23] = 1 199 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 200 * SETA OR[28] = 0 201 * TRLX OR[29] = 1 202 * EHTR OR[30] = 1 203 * EAD extra time OR[31] = 1 204 * 205 * 0 4 8 12 16 20 24 28 206 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 207 */ 208 209 #define CONFIG_FSL_CADMUS 210 211 #define CADMUS_BASE_ADDR 0xf8000000 212 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 213 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 214 215 #define CONFIG_SYS_INIT_RAM_LOCK 1 216 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 217 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 218 219 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 221 222 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 223 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 224 225 /* Serial Port */ 226 #define CONFIG_SYS_NS16550_SERIAL 227 #define CONFIG_SYS_NS16550_REG_SIZE 1 228 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 229 230 #define CONFIG_SYS_BAUDRATE_TABLE \ 231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 232 233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 235 236 /* 237 * I2C 238 */ 239 #define CONFIG_SYS_I2C 240 #define CONFIG_SYS_I2C_FSL 241 #define CONFIG_SYS_FSL_I2C_SPEED 400000 242 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 243 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 244 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 245 246 /* EEPROM */ 247 #define CONFIG_ID_EEPROM 248 #define CONFIG_SYS_I2C_EEPROM_CCID 249 #define CONFIG_SYS_ID_EEPROM 250 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 252 253 /* 254 * General PCI 255 * Addresses are mapped 1-1. 256 */ 257 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 258 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 259 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 261 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 262 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 263 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 264 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 265 266 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 267 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 268 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 269 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 270 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 271 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 272 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 273 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 274 275 #ifdef CONFIG_LEGACY 276 #define BRIDGE_ID 17 277 #define VIA_ID 2 278 #else 279 #define BRIDGE_ID 28 280 #define VIA_ID 4 281 #endif 282 283 #if defined(CONFIG_PCI) 284 285 #define CONFIG_MPC85XX_PCI2 286 287 #undef CONFIG_EEPRO100 288 #undef CONFIG_TULIP 289 290 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 291 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 292 293 #endif /* CONFIG_PCI */ 294 295 #if defined(CONFIG_TSEC_ENET) 296 297 #define CONFIG_TSEC1 1 298 #define CONFIG_TSEC1_NAME "TSEC0" 299 #define CONFIG_TSEC2 1 300 #define CONFIG_TSEC2_NAME "TSEC1" 301 #define TSEC1_PHY_ADDR 0 302 #define TSEC2_PHY_ADDR 1 303 #define TSEC1_PHYIDX 0 304 #define TSEC2_PHYIDX 0 305 #define TSEC1_FLAGS TSEC_GIGABIT 306 #define TSEC2_FLAGS TSEC_GIGABIT 307 308 /* Options are: TSEC[0-1] */ 309 #define CONFIG_ETHPRIME "TSEC0" 310 311 #endif /* CONFIG_TSEC_ENET */ 312 313 /* 314 * Environment 315 */ 316 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 317 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 318 #define CONFIG_ENV_SIZE 0x2000 319 320 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 321 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 322 323 /* 324 * BOOTP options 325 */ 326 #define CONFIG_BOOTP_BOOTFILESIZE 327 328 #undef CONFIG_WATCHDOG /* watchdog disabled */ 329 330 /* 331 * Miscellaneous configurable options 332 */ 333 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 334 335 /* 336 * For booting Linux, the board info and command line data 337 * have to be in the first 64 MB of memory, since this is 338 * the maximum mapped by the Linux kernel during initialization. 339 */ 340 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 341 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 342 343 #if defined(CONFIG_CMD_KGDB) 344 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 345 #endif 346 347 /* 348 * Environment Configuration 349 */ 350 #if defined(CONFIG_TSEC_ENET) 351 #define CONFIG_HAS_ETH0 352 #define CONFIG_HAS_ETH1 353 #define CONFIG_HAS_ETH2 354 #endif 355 356 #define CONFIG_IPADDR 192.168.1.253 357 358 #define CONFIG_HOSTNAME "unknown" 359 #define CONFIG_ROOTPATH "/nfsroot" 360 #define CONFIG_BOOTFILE "your.uImage" 361 362 #define CONFIG_SERVERIP 192.168.1.1 363 #define CONFIG_GATEWAYIP 192.168.1.1 364 #define CONFIG_NETMASK 255.255.255.0 365 366 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 367 368 #define CONFIG_EXTRA_ENV_SETTINGS \ 369 "netdev=eth0\0" \ 370 "consoledev=ttyS1\0" \ 371 "ramdiskaddr=600000\0" \ 372 "ramdiskfile=your.ramdisk.u-boot\0" \ 373 "fdtaddr=400000\0" \ 374 "fdtfile=your.fdt.dtb\0" 375 376 #define CONFIG_NFSBOOTCOMMAND \ 377 "setenv bootargs root=/dev/nfs rw " \ 378 "nfsroot=$serverip:$rootpath " \ 379 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 380 "console=$consoledev,$baudrate $othbootargs;" \ 381 "tftp $loadaddr $bootfile;" \ 382 "tftp $fdtaddr $fdtfile;" \ 383 "bootm $loadaddr - $fdtaddr" 384 385 #define CONFIG_RAMBOOTCOMMAND \ 386 "setenv bootargs root=/dev/ram rw " \ 387 "console=$consoledev,$baudrate $othbootargs;" \ 388 "tftp $ramdiskaddr $ramdiskfile;" \ 389 "tftp $loadaddr $bootfile;" \ 390 "bootm $loadaddr $ramdiskaddr" 391 392 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 393 394 #endif /* __CONFIG_H */ 395