1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8555cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 20 #define CONFIG_CPM2 1 /* has CPM2 */ 21 #define CONFIG_MPC8555 1 /* MPC8555 specific */ 22 #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ 23 24 #define CONFIG_SYS_TEXT_BASE 0xfff80000 25 26 #define CONFIG_PCI 27 #define CONFIG_PCI_INDIRECT_BRIDGE 28 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 29 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 30 #define CONFIG_ENV_OVERWRITE 31 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 32 33 #define CONFIG_FSL_VIA 34 35 36 #ifndef __ASSEMBLY__ 37 extern unsigned long get_clock_freq(void); 38 #endif 39 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 40 41 /* 42 * These can be toggled for performance analysis, otherwise use default. 43 */ 44 #define CONFIG_L2_CACHE /* toggle L2 cache */ 45 #define CONFIG_BTB /* toggle branch predition */ 46 47 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 48 #define CONFIG_SYS_MEMTEST_END 0x00400000 49 50 #define CONFIG_SYS_CCSRBAR 0xe0000000 51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 52 53 /* DDR Setup */ 54 #define CONFIG_FSL_DDR1 55 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 56 #define CONFIG_DDR_SPD 57 #undef CONFIG_FSL_DDR_INTERACTIVE 58 59 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 60 61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 64 #define CONFIG_NUM_DDR_CONTROLLERS 1 65 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 66 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 67 68 /* I2C addresses of SPD EEPROMs */ 69 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 70 71 /* Make sure required options are set */ 72 #ifndef CONFIG_SPD_EEPROM 73 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 74 #endif 75 76 #undef CONFIG_CLOCKS_IN_MHZ 77 78 /* 79 * Local Bus Definitions 80 */ 81 82 /* 83 * FLASH on the Local Bus 84 * Two banks, 8M each, using the CFI driver. 85 * Boot from BR0/OR0 bank at 0xff00_0000 86 * Alternate BR1/OR1 bank at 0xff80_0000 87 * 88 * BR0, BR1: 89 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 90 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 91 * Port Size = 16 bits = BRx[19:20] = 10 92 * Use GPCM = BRx[24:26] = 000 93 * Valid = BRx[31] = 1 94 * 95 * 0 4 8 12 16 20 24 28 96 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 97 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 98 * 99 * OR0, OR1: 100 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 101 * Reserved ORx[17:18] = 11, confusion here? 102 * CSNT = ORx[20] = 1 103 * ACS = half cycle delay = ORx[21:22] = 11 104 * SCY = 6 = ORx[24:27] = 0110 105 * TRLX = use relaxed timing = ORx[29] = 1 106 * EAD = use external address latch delay = OR[31] = 1 107 * 108 * 0 4 8 12 16 20 24 28 109 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 110 */ 111 112 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 113 114 #define CONFIG_SYS_BR0_PRELIM 0xff801001 115 #define CONFIG_SYS_BR1_PRELIM 0xff001001 116 117 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 118 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 119 120 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 121 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 122 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 123 #undef CONFIG_SYS_FLASH_CHECKSUM 124 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 125 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 126 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 128 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_EMPTY_INFO 132 133 134 /* 135 * SDRAM on the Local Bus 136 */ 137 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 138 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 139 140 /* 141 * Base Register 2 and Option Register 2 configure SDRAM. 142 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 143 * 144 * For BR2, need: 145 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 146 * port-size = 32-bits = BR2[19:20] = 11 147 * no parity checking = BR2[21:22] = 00 148 * SDRAM for MSEL = BR2[24:26] = 011 149 * Valid = BR[31] = 1 150 * 151 * 0 4 8 12 16 20 24 28 152 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 153 * 154 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 155 * FIXME: the top 17 bits of BR2. 156 */ 157 158 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 159 160 /* 161 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 162 * 163 * For OR2, need: 164 * 64MB mask for AM, OR2[0:7] = 1111 1100 165 * XAM, OR2[17:18] = 11 166 * 9 columns OR2[19-21] = 010 167 * 13 rows OR2[23-25] = 100 168 * EAD set for extra time OR[31] = 1 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 172 */ 173 174 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 175 176 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 177 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 178 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 179 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 180 181 /* 182 * Common settings for all Local Bus SDRAM commands. 183 * At run time, either BSMA1516 (for CPU 1.1) 184 * or BSMA1617 (for CPU 1.0) (old) 185 * is OR'ed in too. 186 */ 187 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 188 | LSDMR_PRETOACT7 \ 189 | LSDMR_ACTTORW7 \ 190 | LSDMR_BL8 \ 191 | LSDMR_WRC4 \ 192 | LSDMR_CL3 \ 193 | LSDMR_RFEN \ 194 ) 195 196 /* 197 * The CADMUS registers are connected to CS3 on CDS. 198 * The new memory map places CADMUS at 0xf8000000. 199 * 200 * For BR3, need: 201 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 202 * port-size = 8-bits = BR[19:20] = 01 203 * no parity checking = BR[21:22] = 00 204 * GPMC for MSEL = BR[24:26] = 000 205 * Valid = BR[31] = 1 206 * 207 * 0 4 8 12 16 20 24 28 208 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 209 * 210 * For OR3, need: 211 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 212 * disable buffer ctrl OR[19] = 0 213 * CSNT OR[20] = 1 214 * ACS OR[21:22] = 11 215 * XACS OR[23] = 1 216 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 217 * SETA OR[28] = 0 218 * TRLX OR[29] = 1 219 * EHTR OR[30] = 1 220 * EAD extra time OR[31] = 1 221 * 222 * 0 4 8 12 16 20 24 28 223 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 224 */ 225 226 #define CONFIG_FSL_CADMUS 227 228 #define CADMUS_BASE_ADDR 0xf8000000 229 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 230 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 231 232 #define CONFIG_SYS_INIT_RAM_LOCK 1 233 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 234 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 235 236 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 238 239 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 240 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 241 242 /* Serial Port */ 243 #define CONFIG_CONS_INDEX 2 244 #define CONFIG_SYS_NS16550 245 #define CONFIG_SYS_NS16550_SERIAL 246 #define CONFIG_SYS_NS16550_REG_SIZE 1 247 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 248 249 #define CONFIG_SYS_BAUDRATE_TABLE \ 250 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 251 252 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 253 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 254 255 /* Use the HUSH parser */ 256 #define CONFIG_SYS_HUSH_PARSER 257 #ifdef CONFIG_SYS_HUSH_PARSER 258 #endif 259 260 /* pass open firmware flat tree */ 261 #define CONFIG_OF_LIBFDT 1 262 #define CONFIG_OF_BOARD_SETUP 1 263 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 264 265 /* 266 * I2C 267 */ 268 #define CONFIG_SYS_I2C 269 #define CONFIG_SYS_I2C_FSL 270 #define CONFIG_SYS_FSL_I2C_SPEED 400000 271 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 272 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 273 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 274 275 /* EEPROM */ 276 #define CONFIG_ID_EEPROM 277 #define CONFIG_SYS_I2C_EEPROM_CCID 278 #define CONFIG_SYS_ID_EEPROM 279 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 280 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 281 282 /* 283 * General PCI 284 * Addresses are mapped 1-1. 285 */ 286 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 287 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 288 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 289 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 290 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 291 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 292 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 293 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 294 295 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 296 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 297 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 298 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 299 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 300 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 301 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 302 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 303 304 #ifdef CONFIG_LEGACY 305 #define BRIDGE_ID 17 306 #define VIA_ID 2 307 #else 308 #define BRIDGE_ID 28 309 #define VIA_ID 4 310 #endif 311 312 #if defined(CONFIG_PCI) 313 314 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 315 #define CONFIG_MPC85XX_PCI2 316 317 #undef CONFIG_EEPRO100 318 #undef CONFIG_TULIP 319 320 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 321 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 322 323 #endif /* CONFIG_PCI */ 324 325 326 #if defined(CONFIG_TSEC_ENET) 327 328 #define CONFIG_MII 1 /* MII PHY management */ 329 #define CONFIG_TSEC1 1 330 #define CONFIG_TSEC1_NAME "TSEC0" 331 #define CONFIG_TSEC2 1 332 #define CONFIG_TSEC2_NAME "TSEC1" 333 #define TSEC1_PHY_ADDR 0 334 #define TSEC2_PHY_ADDR 1 335 #define TSEC1_PHYIDX 0 336 #define TSEC2_PHYIDX 0 337 #define TSEC1_FLAGS TSEC_GIGABIT 338 #define TSEC2_FLAGS TSEC_GIGABIT 339 340 /* Options are: TSEC[0-1] */ 341 #define CONFIG_ETHPRIME "TSEC0" 342 343 #endif /* CONFIG_TSEC_ENET */ 344 345 /* 346 * Environment 347 */ 348 #define CONFIG_ENV_IS_IN_FLASH 1 349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 350 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 351 #define CONFIG_ENV_SIZE 0x2000 352 353 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 354 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 355 356 /* 357 * BOOTP options 358 */ 359 #define CONFIG_BOOTP_BOOTFILESIZE 360 #define CONFIG_BOOTP_BOOTPATH 361 #define CONFIG_BOOTP_GATEWAY 362 #define CONFIG_BOOTP_HOSTNAME 363 364 365 /* 366 * Command line configuration. 367 */ 368 #include <config_cmd_default.h> 369 370 #define CONFIG_CMD_PING 371 #define CONFIG_CMD_I2C 372 #define CONFIG_CMD_MII 373 #define CONFIG_CMD_ELF 374 #define CONFIG_CMD_IRQ 375 #define CONFIG_CMD_SETEXPR 376 #define CONFIG_CMD_REGINFO 377 378 #if defined(CONFIG_PCI) 379 #define CONFIG_CMD_PCI 380 #endif 381 382 383 #undef CONFIG_WATCHDOG /* watchdog disabled */ 384 385 /* 386 * Miscellaneous configurable options 387 */ 388 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 389 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 390 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 391 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 392 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 393 #if defined(CONFIG_CMD_KGDB) 394 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 395 #else 396 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 397 #endif 398 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 399 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 400 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 401 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 402 403 /* 404 * For booting Linux, the board info and command line data 405 * have to be in the first 64 MB of memory, since this is 406 * the maximum mapped by the Linux kernel during initialization. 407 */ 408 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 409 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 410 411 #if defined(CONFIG_CMD_KGDB) 412 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 413 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 414 #endif 415 416 /* 417 * Environment Configuration 418 */ 419 420 /* The mac addresses for all ethernet interface */ 421 #if defined(CONFIG_TSEC_ENET) 422 #define CONFIG_HAS_ETH0 423 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 424 #define CONFIG_HAS_ETH1 425 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 426 #define CONFIG_HAS_ETH2 427 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 428 #endif 429 430 #define CONFIG_IPADDR 192.168.1.253 431 432 #define CONFIG_HOSTNAME unknown 433 #define CONFIG_ROOTPATH "/nfsroot" 434 #define CONFIG_BOOTFILE "your.uImage" 435 436 #define CONFIG_SERVERIP 192.168.1.1 437 #define CONFIG_GATEWAYIP 192.168.1.1 438 #define CONFIG_NETMASK 255.255.255.0 439 440 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 441 442 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 443 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 444 445 #define CONFIG_BAUDRATE 115200 446 447 #define CONFIG_EXTRA_ENV_SETTINGS \ 448 "netdev=eth0\0" \ 449 "consoledev=ttyS1\0" \ 450 "ramdiskaddr=600000\0" \ 451 "ramdiskfile=your.ramdisk.u-boot\0" \ 452 "fdtaddr=400000\0" \ 453 "fdtfile=your.fdt.dtb\0" 454 455 #define CONFIG_NFSBOOTCOMMAND \ 456 "setenv bootargs root=/dev/nfs rw " \ 457 "nfsroot=$serverip:$rootpath " \ 458 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 459 "console=$consoledev,$baudrate $othbootargs;" \ 460 "tftp $loadaddr $bootfile;" \ 461 "tftp $fdtaddr $fdtfile;" \ 462 "bootm $loadaddr - $fdtaddr" 463 464 #define CONFIG_RAMBOOTCOMMAND \ 465 "setenv bootargs root=/dev/ram rw " \ 466 "console=$consoledev,$baudrate $othbootargs;" \ 467 "tftp $ramdiskaddr $ramdiskfile;" \ 468 "tftp $loadaddr $bootfile;" \ 469 "bootm $loadaddr $ramdiskaddr" 470 471 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 472 473 #endif /* __CONFIG_H */ 474