1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8555cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 36 #define CONFIG_CPM2 1 /* has CPM2 */ 37 #define CONFIG_MPC8555 1 /* MPC8555 specific */ 38 #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ 39 40 #define CONFIG_SYS_TEXT_BASE 0xfff80000 41 42 #define CONFIG_PCI 43 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 44 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 45 #define CONFIG_ENV_OVERWRITE 46 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 47 48 #define CONFIG_FSL_VIA 49 50 51 #ifndef __ASSEMBLY__ 52 extern unsigned long get_clock_freq(void); 53 #endif 54 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 55 56 /* 57 * These can be toggled for performance analysis, otherwise use default. 58 */ 59 #define CONFIG_L2_CACHE /* toggle L2 cache */ 60 #define CONFIG_BTB /* toggle branch predition */ 61 62 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 63 #define CONFIG_SYS_MEMTEST_END 0x00400000 64 65 /* 66 * Base addresses -- Note these are effective addresses where the 67 * actual resources get mapped (not physical addresses) 68 */ 69 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 70 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 71 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 72 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 73 74 /* DDR Setup */ 75 #define CONFIG_FSL_DDR1 76 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 77 #define CONFIG_DDR_SPD 78 #undef CONFIG_FSL_DDR_INTERACTIVE 79 80 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 81 82 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 83 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 84 85 #define CONFIG_NUM_DDR_CONTROLLERS 1 86 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 87 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 88 89 /* I2C addresses of SPD EEPROMs */ 90 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 91 92 /* Make sure required options are set */ 93 #ifndef CONFIG_SPD_EEPROM 94 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 95 #endif 96 97 #undef CONFIG_CLOCKS_IN_MHZ 98 99 /* 100 * Local Bus Definitions 101 */ 102 103 /* 104 * FLASH on the Local Bus 105 * Two banks, 8M each, using the CFI driver. 106 * Boot from BR0/OR0 bank at 0xff00_0000 107 * Alternate BR1/OR1 bank at 0xff80_0000 108 * 109 * BR0, BR1: 110 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 111 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 112 * Port Size = 16 bits = BRx[19:20] = 10 113 * Use GPCM = BRx[24:26] = 000 114 * Valid = BRx[31] = 1 115 * 116 * 0 4 8 12 16 20 24 28 117 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 118 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 119 * 120 * OR0, OR1: 121 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 122 * Reserved ORx[17:18] = 11, confusion here? 123 * CSNT = ORx[20] = 1 124 * ACS = half cycle delay = ORx[21:22] = 11 125 * SCY = 6 = ORx[24:27] = 0110 126 * TRLX = use relaxed timing = ORx[29] = 1 127 * EAD = use external address latch delay = OR[31] = 1 128 * 129 * 0 4 8 12 16 20 24 28 130 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 131 */ 132 133 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 134 135 #define CONFIG_SYS_BR0_PRELIM 0xff801001 136 #define CONFIG_SYS_BR1_PRELIM 0xff001001 137 138 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 139 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 140 141 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 142 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 143 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 144 #undef CONFIG_SYS_FLASH_CHECKSUM 145 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 146 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 147 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 149 150 #define CONFIG_FLASH_CFI_DRIVER 151 #define CONFIG_SYS_FLASH_CFI 152 #define CONFIG_SYS_FLASH_EMPTY_INFO 153 154 155 /* 156 * SDRAM on the Local Bus 157 */ 158 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 159 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 160 161 /* 162 * Base Register 2 and Option Register 2 configure SDRAM. 163 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 164 * 165 * For BR2, need: 166 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 167 * port-size = 32-bits = BR2[19:20] = 11 168 * no parity checking = BR2[21:22] = 00 169 * SDRAM for MSEL = BR2[24:26] = 011 170 * Valid = BR[31] = 1 171 * 172 * 0 4 8 12 16 20 24 28 173 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 174 * 175 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 176 * FIXME: the top 17 bits of BR2. 177 */ 178 179 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 180 181 /* 182 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 183 * 184 * For OR2, need: 185 * 64MB mask for AM, OR2[0:7] = 1111 1100 186 * XAM, OR2[17:18] = 11 187 * 9 columns OR2[19-21] = 010 188 * 13 rows OR2[23-25] = 100 189 * EAD set for extra time OR[31] = 1 190 * 191 * 0 4 8 12 16 20 24 28 192 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 193 */ 194 195 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 196 197 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 198 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 199 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 200 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 201 202 /* 203 * Common settings for all Local Bus SDRAM commands. 204 * At run time, either BSMA1516 (for CPU 1.1) 205 * or BSMA1617 (for CPU 1.0) (old) 206 * is OR'ed in too. 207 */ 208 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 209 | LSDMR_PRETOACT7 \ 210 | LSDMR_ACTTORW7 \ 211 | LSDMR_BL8 \ 212 | LSDMR_WRC4 \ 213 | LSDMR_CL3 \ 214 | LSDMR_RFEN \ 215 ) 216 217 /* 218 * The CADMUS registers are connected to CS3 on CDS. 219 * The new memory map places CADMUS at 0xf8000000. 220 * 221 * For BR3, need: 222 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 223 * port-size = 8-bits = BR[19:20] = 01 224 * no parity checking = BR[21:22] = 00 225 * GPMC for MSEL = BR[24:26] = 000 226 * Valid = BR[31] = 1 227 * 228 * 0 4 8 12 16 20 24 28 229 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 230 * 231 * For OR3, need: 232 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 233 * disable buffer ctrl OR[19] = 0 234 * CSNT OR[20] = 1 235 * ACS OR[21:22] = 11 236 * XACS OR[23] = 1 237 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 238 * SETA OR[28] = 0 239 * TRLX OR[29] = 1 240 * EHTR OR[30] = 1 241 * EAD extra time OR[31] = 1 242 * 243 * 0 4 8 12 16 20 24 28 244 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 245 */ 246 247 #define CONFIG_FSL_CADMUS 248 249 #define CADMUS_BASE_ADDR 0xf8000000 250 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 251 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 252 253 #define CONFIG_SYS_INIT_RAM_LOCK 1 254 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 255 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 256 257 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 258 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 259 260 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 261 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 262 263 /* Serial Port */ 264 #define CONFIG_CONS_INDEX 2 265 #define CONFIG_SYS_NS16550 266 #define CONFIG_SYS_NS16550_SERIAL 267 #define CONFIG_SYS_NS16550_REG_SIZE 1 268 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 269 270 #define CONFIG_SYS_BAUDRATE_TABLE \ 271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 272 273 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 274 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 275 276 /* Use the HUSH parser */ 277 #define CONFIG_SYS_HUSH_PARSER 278 #ifdef CONFIG_SYS_HUSH_PARSER 279 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 280 #endif 281 282 /* pass open firmware flat tree */ 283 #define CONFIG_OF_LIBFDT 1 284 #define CONFIG_OF_BOARD_SETUP 1 285 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 286 287 /* 288 * I2C 289 */ 290 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 291 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 292 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 293 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 294 #define CONFIG_SYS_I2C_SLAVE 0x7F 295 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 296 #define CONFIG_SYS_I2C_OFFSET 0x3000 297 298 /* EEPROM */ 299 #define CONFIG_ID_EEPROM 300 #define CONFIG_SYS_I2C_EEPROM_CCID 301 #define CONFIG_SYS_ID_EEPROM 302 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 303 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 304 305 /* 306 * General PCI 307 * Addresses are mapped 1-1. 308 */ 309 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 310 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 311 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 312 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 313 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 314 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 315 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 316 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 317 318 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 319 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 320 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 321 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 322 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 323 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 324 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 325 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 326 327 #ifdef CONFIG_LEGACY 328 #define BRIDGE_ID 17 329 #define VIA_ID 2 330 #else 331 #define BRIDGE_ID 28 332 #define VIA_ID 4 333 #endif 334 335 #if defined(CONFIG_PCI) 336 337 #define CONFIG_NET_MULTI 338 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 339 #define CONFIG_MPC85XX_PCI2 340 341 #undef CONFIG_EEPRO100 342 #undef CONFIG_TULIP 343 344 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 345 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 346 347 #endif /* CONFIG_PCI */ 348 349 350 #if defined(CONFIG_TSEC_ENET) 351 352 #ifndef CONFIG_NET_MULTI 353 #define CONFIG_NET_MULTI 1 354 #endif 355 356 #define CONFIG_MII 1 /* MII PHY management */ 357 #define CONFIG_TSEC1 1 358 #define CONFIG_TSEC1_NAME "TSEC0" 359 #define CONFIG_TSEC2 1 360 #define CONFIG_TSEC2_NAME "TSEC1" 361 #define TSEC1_PHY_ADDR 0 362 #define TSEC2_PHY_ADDR 1 363 #define TSEC1_PHYIDX 0 364 #define TSEC2_PHYIDX 0 365 #define TSEC1_FLAGS TSEC_GIGABIT 366 #define TSEC2_FLAGS TSEC_GIGABIT 367 368 /* Options are: TSEC[0-1] */ 369 #define CONFIG_ETHPRIME "TSEC0" 370 371 #endif /* CONFIG_TSEC_ENET */ 372 373 /* 374 * Environment 375 */ 376 #define CONFIG_ENV_IS_IN_FLASH 1 377 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 378 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 379 #define CONFIG_ENV_SIZE 0x2000 380 381 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 382 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 383 384 /* 385 * BOOTP options 386 */ 387 #define CONFIG_BOOTP_BOOTFILESIZE 388 #define CONFIG_BOOTP_BOOTPATH 389 #define CONFIG_BOOTP_GATEWAY 390 #define CONFIG_BOOTP_HOSTNAME 391 392 393 /* 394 * Command line configuration. 395 */ 396 #include <config_cmd_default.h> 397 398 #define CONFIG_CMD_PING 399 #define CONFIG_CMD_I2C 400 #define CONFIG_CMD_MII 401 #define CONFIG_CMD_ELF 402 #define CONFIG_CMD_IRQ 403 #define CONFIG_CMD_SETEXPR 404 #define CONFIG_CMD_REGINFO 405 406 #if defined(CONFIG_PCI) 407 #define CONFIG_CMD_PCI 408 #endif 409 410 411 #undef CONFIG_WATCHDOG /* watchdog disabled */ 412 413 /* 414 * Miscellaneous configurable options 415 */ 416 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 417 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 418 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 419 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 420 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 421 #if defined(CONFIG_CMD_KGDB) 422 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 423 #else 424 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 425 #endif 426 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 427 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 428 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 429 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 430 431 /* 432 * For booting Linux, the board info and command line data 433 * have to be in the first 16 MB of memory, since this is 434 * the maximum mapped by the Linux kernel during initialization. 435 */ 436 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 437 438 #if defined(CONFIG_CMD_KGDB) 439 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 440 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 441 #endif 442 443 /* 444 * Environment Configuration 445 */ 446 447 /* The mac addresses for all ethernet interface */ 448 #if defined(CONFIG_TSEC_ENET) 449 #define CONFIG_HAS_ETH0 450 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 451 #define CONFIG_HAS_ETH1 452 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 453 #define CONFIG_HAS_ETH2 454 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 455 #endif 456 457 #define CONFIG_IPADDR 192.168.1.253 458 459 #define CONFIG_HOSTNAME unknown 460 #define CONFIG_ROOTPATH /nfsroot 461 #define CONFIG_BOOTFILE your.uImage 462 463 #define CONFIG_SERVERIP 192.168.1.1 464 #define CONFIG_GATEWAYIP 192.168.1.1 465 #define CONFIG_NETMASK 255.255.255.0 466 467 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 468 469 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 470 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 471 472 #define CONFIG_BAUDRATE 115200 473 474 #define CONFIG_EXTRA_ENV_SETTINGS \ 475 "netdev=eth0\0" \ 476 "consoledev=ttyS1\0" \ 477 "ramdiskaddr=600000\0" \ 478 "ramdiskfile=your.ramdisk.u-boot\0" \ 479 "fdtaddr=400000\0" \ 480 "fdtfile=your.fdt.dtb\0" 481 482 #define CONFIG_NFSBOOTCOMMAND \ 483 "setenv bootargs root=/dev/nfs rw " \ 484 "nfsroot=$serverip:$rootpath " \ 485 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 486 "console=$consoledev,$baudrate $othbootargs;" \ 487 "tftp $loadaddr $bootfile;" \ 488 "tftp $fdtaddr $fdtfile;" \ 489 "bootm $loadaddr - $fdtaddr" 490 491 #define CONFIG_RAMBOOTCOMMAND \ 492 "setenv bootargs root=/dev/ram rw " \ 493 "console=$consoledev,$baudrate $othbootargs;" \ 494 "tftp $ramdiskaddr $ramdiskfile;" \ 495 "tftp $loadaddr $bootfile;" \ 496 "bootm $loadaddr $ramdiskaddr" 497 498 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 499 500 #endif /* __CONFIG_H */ 501