1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xfff80000 41 #endif 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 46 #define CONFIG_PCI /* enable any pci type devices */ 47 #define CONFIG_PCI1 /* PCI controller 1 */ 48 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 49 #undef CONFIG_PCI2 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 58 59 #define CONFIG_FSL_VIA 60 61 #ifndef __ASSEMBLY__ 62 extern unsigned long get_clock_freq(void); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 #define CONFIG_SYS_CCSRBAR 0xe0000000 81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 82 83 /* DDR Setup */ 84 #define CONFIG_FSL_DDR2 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 87 #define CONFIG_DDR_SPD 88 89 #define CONFIG_DDR_ECC 90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 92 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_NUM_DDR_CONTROLLERS 1 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 98 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 99 100 /* I2C addresses of SPD EEPROMs */ 101 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 102 103 /* Make sure required options are set */ 104 #ifndef CONFIG_SPD_EEPROM 105 #error ("CONFIG_SPD_EEPROM is required") 106 #endif 107 108 #undef CONFIG_CLOCKS_IN_MHZ 109 /* 110 * Physical Address Map 111 * 112 * 32bit: 113 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 114 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 115 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 116 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 117 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 118 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 119 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 120 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 121 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 122 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 123 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 124 * 125 */ 126 127 128 /* 129 * Local Bus Definitions 130 */ 131 132 /* 133 * FLASH on the Local Bus 134 * Two banks, 8M each, using the CFI driver. 135 * Boot from BR0/OR0 bank at 0xff00_0000 136 * Alternate BR1/OR1 bank at 0xff80_0000 137 * 138 * BR0, BR1: 139 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 140 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 141 * Port Size = 16 bits = BRx[19:20] = 10 142 * Use GPCM = BRx[24:26] = 000 143 * Valid = BRx[31] = 1 144 * 145 * 0 4 8 12 16 20 24 28 146 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 147 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 148 * 149 * OR0, OR1: 150 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 151 * Reserved ORx[17:18] = 11, confusion here? 152 * CSNT = ORx[20] = 1 153 * ACS = half cycle delay = ORx[21:22] = 11 154 * SCY = 6 = ORx[24:27] = 0110 155 * TRLX = use relaxed timing = ORx[29] = 1 156 * EAD = use external address latch delay = OR[31] = 1 157 * 158 * 0 4 8 12 16 20 24 28 159 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 160 */ 161 162 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 163 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 164 165 #define CONFIG_SYS_BR0_PRELIM \ 166 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \ 167 | BR_PS_16 | BR_V) 168 #define CONFIG_SYS_BR1_PRELIM \ 169 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 170 171 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 172 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 173 174 #define CONFIG_SYS_FLASH_BANKS_LIST \ 175 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 176 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 177 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 178 #undef CONFIG_SYS_FLASH_CHECKSUM 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 183 184 #define CONFIG_FLASH_CFI_DRIVER 185 #define CONFIG_SYS_FLASH_CFI 186 #define CONFIG_SYS_FLASH_EMPTY_INFO 187 188 #define CONFIG_HWCONFIG /* enable hwconfig */ 189 190 /* 191 * SDRAM on the Local Bus 192 */ 193 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 194 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 195 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 196 197 /* 198 * Base Register 2 and Option Register 2 configure SDRAM. 199 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 200 * 201 * For BR2, need: 202 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 203 * port-size = 32-bits = BR2[19:20] = 11 204 * no parity checking = BR2[21:22] = 00 205 * SDRAM for MSEL = BR2[24:26] = 011 206 * Valid = BR[31] = 1 207 * 208 * 0 4 8 12 16 20 24 28 209 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 210 * 211 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 212 * FIXME: the top 17 bits of BR2. 213 */ 214 215 #define CONFIG_SYS_BR2_PRELIM \ 216 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 217 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 218 219 /* 220 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 221 * 222 * For OR2, need: 223 * 64MB mask for AM, OR2[0:7] = 1111 1100 224 * XAM, OR2[17:18] = 11 225 * 9 columns OR2[19-21] = 010 226 * 13 rows OR2[23-25] = 100 227 * EAD set for extra time OR[31] = 1 228 * 229 * 0 4 8 12 16 20 24 28 230 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 231 */ 232 233 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 234 235 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 236 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 237 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 238 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 239 240 /* 241 * Common settings for all Local Bus SDRAM commands. 242 * At run time, either BSMA1516 (for CPU 1.1) 243 * or BSMA1617 (for CPU 1.0) (old) 244 * is OR'ed in too. 245 */ 246 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 247 | LSDMR_PRETOACT7 \ 248 | LSDMR_ACTTORW7 \ 249 | LSDMR_BL8 \ 250 | LSDMR_WRC4 \ 251 | LSDMR_CL3 \ 252 | LSDMR_RFEN \ 253 ) 254 255 /* 256 * The CADMUS registers are connected to CS3 on CDS. 257 * The new memory map places CADMUS at 0xf8000000. 258 * 259 * For BR3, need: 260 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 261 * port-size = 8-bits = BR[19:20] = 01 262 * no parity checking = BR[21:22] = 00 263 * GPMC for MSEL = BR[24:26] = 000 264 * Valid = BR[31] = 1 265 * 266 * 0 4 8 12 16 20 24 28 267 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 268 * 269 * For OR3, need: 270 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 271 * disable buffer ctrl OR[19] = 0 272 * CSNT OR[20] = 1 273 * ACS OR[21:22] = 11 274 * XACS OR[23] = 1 275 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 276 * SETA OR[28] = 0 277 * TRLX OR[29] = 1 278 * EHTR OR[30] = 1 279 * EAD extra time OR[31] = 1 280 * 281 * 0 4 8 12 16 20 24 28 282 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 283 */ 284 285 #define CONFIG_FSL_CADMUS 286 287 #define CADMUS_BASE_ADDR 0xf8000000 288 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 289 #define CONFIG_SYS_BR3_PRELIM \ 290 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 291 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 292 293 #define CONFIG_SYS_INIT_RAM_LOCK 1 294 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 295 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 296 297 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 298 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 299 300 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 301 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 302 303 /* Serial Port */ 304 #define CONFIG_CONS_INDEX 2 305 #define CONFIG_SYS_NS16550 306 #define CONFIG_SYS_NS16550_SERIAL 307 #define CONFIG_SYS_NS16550_REG_SIZE 1 308 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 309 310 #define CONFIG_SYS_BAUDRATE_TABLE \ 311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 312 313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 315 316 /* Use the HUSH parser */ 317 #define CONFIG_SYS_HUSH_PARSER 318 #ifdef CONFIG_SYS_HUSH_PARSER 319 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 320 #endif 321 322 /* pass open firmware flat tree */ 323 #define CONFIG_OF_LIBFDT 1 324 #define CONFIG_OF_BOARD_SETUP 1 325 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 326 327 /* 328 * I2C 329 */ 330 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 331 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 332 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 333 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 334 #define CONFIG_SYS_I2C_SLAVE 0x7F 335 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 336 #define CONFIG_SYS_I2C_OFFSET 0x3000 337 338 /* EEPROM */ 339 #define CONFIG_ID_EEPROM 340 #define CONFIG_SYS_I2C_EEPROM_CCID 341 #define CONFIG_SYS_ID_EEPROM 342 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 343 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 344 345 /* 346 * General PCI 347 * Memory space is mapped 1-1, but I/O space must start from 0. 348 */ 349 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 350 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 351 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 352 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 353 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 354 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 355 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 356 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 357 358 #ifdef CONFIG_PCIE1 359 #define CONFIG_SYS_PCIE1_NAME "Slot" 360 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 361 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 362 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 363 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 364 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 365 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 366 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 367 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 368 #endif 369 370 /* 371 * RapidIO MMU 372 */ 373 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 374 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 375 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 376 377 #ifdef CONFIG_LEGACY 378 #define BRIDGE_ID 17 379 #define VIA_ID 2 380 #else 381 #define BRIDGE_ID 28 382 #define VIA_ID 4 383 #endif 384 385 #if defined(CONFIG_PCI) 386 387 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 388 389 #undef CONFIG_EEPRO100 390 #undef CONFIG_TULIP 391 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 392 393 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 394 395 #endif /* CONFIG_PCI */ 396 397 398 #if defined(CONFIG_TSEC_ENET) 399 400 #define CONFIG_MII 1 /* MII PHY management */ 401 #define CONFIG_TSEC1 1 402 #define CONFIG_TSEC1_NAME "eTSEC0" 403 #define CONFIG_TSEC2 1 404 #define CONFIG_TSEC2_NAME "eTSEC1" 405 #define CONFIG_TSEC3 1 406 #define CONFIG_TSEC3_NAME "eTSEC2" 407 #define CONFIG_TSEC4 408 #define CONFIG_TSEC4_NAME "eTSEC3" 409 #undef CONFIG_MPC85XX_FEC 410 411 #define TSEC1_PHY_ADDR 0 412 #define TSEC2_PHY_ADDR 1 413 #define TSEC3_PHY_ADDR 2 414 #define TSEC4_PHY_ADDR 3 415 416 #define TSEC1_PHYIDX 0 417 #define TSEC2_PHYIDX 0 418 #define TSEC3_PHYIDX 0 419 #define TSEC4_PHYIDX 0 420 #define TSEC1_FLAGS TSEC_GIGABIT 421 #define TSEC2_FLAGS TSEC_GIGABIT 422 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 424 425 /* Options are: eTSEC[0-3] */ 426 #define CONFIG_ETHPRIME "eTSEC0" 427 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 428 #endif /* CONFIG_TSEC_ENET */ 429 430 /* 431 * Environment 432 */ 433 #define CONFIG_ENV_IS_IN_FLASH 1 434 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 435 #define CONFIG_ENV_ADDR 0xfff80000 436 #else 437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 438 #endif 439 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 440 #define CONFIG_ENV_SIZE 0x2000 441 442 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 444 445 /* 446 * BOOTP options 447 */ 448 #define CONFIG_BOOTP_BOOTFILESIZE 449 #define CONFIG_BOOTP_BOOTPATH 450 #define CONFIG_BOOTP_GATEWAY 451 #define CONFIG_BOOTP_HOSTNAME 452 453 454 /* 455 * Command line configuration. 456 */ 457 #include <config_cmd_default.h> 458 459 #define CONFIG_CMD_PING 460 #define CONFIG_CMD_I2C 461 #define CONFIG_CMD_MII 462 #define CONFIG_CMD_ELF 463 #define CONFIG_CMD_IRQ 464 #define CONFIG_CMD_SETEXPR 465 #define CONFIG_CMD_REGINFO 466 467 #if defined(CONFIG_PCI) 468 #define CONFIG_CMD_PCI 469 #endif 470 471 472 #undef CONFIG_WATCHDOG /* watchdog disabled */ 473 474 /* 475 * Miscellaneous configurable options 476 */ 477 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 478 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 479 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 480 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 481 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 482 #if defined(CONFIG_CMD_KGDB) 483 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 484 #else 485 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 486 #endif 487 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 488 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 489 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 490 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 491 492 /* 493 * For booting Linux, the board info and command line data 494 * have to be in the first 64 MB of memory, since this is 495 * the maximum mapped by the Linux kernel during initialization. 496 */ 497 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 498 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 499 500 #if defined(CONFIG_CMD_KGDB) 501 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 502 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 503 #endif 504 505 /* 506 * Environment Configuration 507 */ 508 509 /* The mac addresses for all ethernet interface */ 510 #if defined(CONFIG_TSEC_ENET) 511 #define CONFIG_HAS_ETH0 512 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 513 #define CONFIG_HAS_ETH1 514 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 515 #define CONFIG_HAS_ETH2 516 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 517 #define CONFIG_HAS_ETH3 518 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 519 #endif 520 521 #define CONFIG_IPADDR 192.168.1.253 522 523 #define CONFIG_HOSTNAME unknown 524 #define CONFIG_ROOTPATH /nfsroot 525 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 526 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 527 528 #define CONFIG_SERVERIP 192.168.1.1 529 #define CONFIG_GATEWAYIP 192.168.1.1 530 #define CONFIG_NETMASK 255.255.255.0 531 532 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 533 534 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 535 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 536 537 #define CONFIG_BAUDRATE 115200 538 539 #define CONFIG_EXTRA_ENV_SETTINGS \ 540 "hwconfig=fsl_ddr:ecc=off\0" \ 541 "netdev=eth0\0" \ 542 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 543 "tftpflash=tftpboot $loadaddr $uboot; " \ 544 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 545 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 546 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 547 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 548 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 549 "consoledev=ttyS1\0" \ 550 "ramdiskaddr=2000000\0" \ 551 "ramdiskfile=ramdisk.uboot\0" \ 552 "fdtaddr=c00000\0" \ 553 "fdtfile=mpc8548cds.dtb\0" 554 555 #define CONFIG_NFSBOOTCOMMAND \ 556 "setenv bootargs root=/dev/nfs rw " \ 557 "nfsroot=$serverip:$rootpath " \ 558 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 559 "console=$consoledev,$baudrate $othbootargs;" \ 560 "tftp $loadaddr $bootfile;" \ 561 "tftp $fdtaddr $fdtfile;" \ 562 "bootm $loadaddr - $fdtaddr" 563 564 565 #define CONFIG_RAMBOOTCOMMAND \ 566 "setenv bootargs root=/dev/ram rw " \ 567 "console=$consoledev,$baudrate $othbootargs;" \ 568 "tftp $ramdiskaddr $ramdiskfile;" \ 569 "tftp $loadaddr $bootfile;" \ 570 "tftp $fdtaddr $fdtfile;" \ 571 "bootm $loadaddr $ramdiskaddr $fdtaddr" 572 573 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 574 575 #endif /* __CONFIG_H */ 576