xref: /openbmc/u-boot/include/configs/MPC8548CDS.h (revision ee52b188)
1 /*
2  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  * mpc8548cds board configuration file
25  *
26  * Please refer to doc/README.mpc85xxcds for more info.
27  *
28  */
29 #ifndef __CONFIG_H
30 #define __CONFIG_H
31 
32 #ifdef CONFIG_36BIT
33 #define CONFIG_PHYS_64BIT
34 #endif
35 
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE		1	/* BOOKE */
38 #define CONFIG_E500		1	/* BOOKE e500 family */
39 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
40 #define CONFIG_MPC8548		1	/* MPC8548 specific */
41 #define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
42 
43 #ifndef CONFIG_SYS_TEXT_BASE
44 #define CONFIG_SYS_TEXT_BASE	0xfff80000
45 #endif
46 
47 #define CONFIG_SYS_SRIO
48 #define CONFIG_SRIO1			/* SRIO port 1 */
49 
50 #define CONFIG_PCI		/* enable any pci type devices */
51 #define CONFIG_PCI1		/* PCI controller 1 */
52 #define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
53 #undef CONFIG_PCI2
54 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
55 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
56 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
57 
58 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
59 #define CONFIG_ENV_OVERWRITE
60 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
61 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
62 
63 #define CONFIG_FSL_VIA
64 
65 #ifndef __ASSEMBLY__
66 extern unsigned long get_clock_freq(void);
67 #endif
68 #define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
69 
70 /*
71  * These can be toggled for performance analysis, otherwise use default.
72  */
73 #define CONFIG_L2_CACHE			/* toggle L2 cache */
74 #define CONFIG_BTB			/* toggle branch predition */
75 
76 /*
77  * Only possible on E500 Version 2 or newer cores.
78  */
79 #define CONFIG_ENABLE_36BIT_PHYS	1
80 
81 #ifdef CONFIG_PHYS_64BIT
82 #define CONFIG_ADDR_MAP
83 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
84 #endif
85 
86 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
87 #define CONFIG_SYS_MEMTEST_END		0x00400000
88 
89 #define CONFIG_SYS_CCSRBAR		0xe0000000
90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
91 
92 /* DDR Setup */
93 #define CONFIG_FSL_DDR2
94 #undef CONFIG_FSL_DDR_INTERACTIVE
95 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
96 #define CONFIG_DDR_SPD
97 
98 #define CONFIG_DDR_ECC
99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
100 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
101 
102 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
103 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
104 
105 #define CONFIG_NUM_DDR_CONTROLLERS	1
106 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
107 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
108 
109 /* I2C addresses of SPD EEPROMs */
110 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
111 
112 /* Make sure required options are set */
113 #ifndef CONFIG_SPD_EEPROM
114 #error ("CONFIG_SPD_EEPROM is required")
115 #endif
116 
117 #undef CONFIG_CLOCKS_IN_MHZ
118 /*
119  * Physical Address Map
120  *
121  * 32bit:
122  * 0x0000_0000	0x7fff_ffff	DDR			2G	cacheable
123  * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M	cacheable
124  * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M	cacheable
125  * 0xc000_0000	0xdfff_ffff	RapidIO			512M	cacheable
126  * 0xe000_0000	0xe00f_ffff	CCSR			1M	non-cacheable
127  * 0xe200_0000	0xe20f_ffff	PCI1 IO			1M	non-cacheable
128  * 0xe300_0000	0xe30f_ffff	PCIe IO			1M	non-cacheable
129  * 0xf000_0000	0xf3ff_ffff	SDRAM			64M	cacheable
130  * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS		1M	non-cacheable
131  * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
132  * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M	non-cacheable
133  *
134  * 36bit:
135  * 0x00000_0000	0x07fff_ffff	DDR			2G	cacheable
136  * 0xc0000_0000	0xc1fff_ffff	PCI1 MEM		512M	cacheable
137  * 0xc2000_0000	0xc3fff_ffff	PCIe MEM		512M	cacheable
138  * 0xc4000_0000	0xc5fff_ffff	RapidIO			512M	cacheable
139  * 0xfe000_0000	0xfe00f_ffff	CCSR			1M	non-cacheable
140  * 0xfe200_0000	0xfe20f_ffff	PCI1 IO			1M	non-cacheable
141  * 0xfe300_0000	0xfe30f_ffff	PCIe IO			1M	non-cacheable
142  * 0xff000_0000	0xff3ff_ffff	SDRAM			64M	cacheable
143  * 0xff800_0000	0xff80f_ffff	NVRAM/CADMUS		1M	non-cacheable
144  * 0xfff00_0000	0xfff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
145  * 0xfff80_0000	0xfffff_ffff	FLASH (boot bank)	8M	non-cacheable
146  *
147  */
148 
149 
150 /*
151  * Local Bus Definitions
152  */
153 
154 /*
155  * FLASH on the Local Bus
156  * Two banks, 8M each, using the CFI driver.
157  * Boot from BR0/OR0 bank at 0xff00_0000
158  * Alternate BR1/OR1 bank at 0xff80_0000
159  *
160  * BR0, BR1:
161  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
162  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
163  *    Port Size = 16 bits = BRx[19:20] = 10
164  *    Use GPCM = BRx[24:26] = 000
165  *    Valid = BRx[31] = 1
166  *
167  * 0	4    8	  12   16   20	 24   28
168  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001	 BR0
169  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001	 BR1
170  *
171  * OR0, OR1:
172  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
173  *    Reserved ORx[17:18] = 11, confusion here?
174  *    CSNT = ORx[20] = 1
175  *    ACS = half cycle delay = ORx[21:22] = 11
176  *    SCY = 6 = ORx[24:27] = 0110
177  *    TRLX = use relaxed timing = ORx[29] = 1
178  *    EAD = use external address latch delay = OR[31] = 1
179  *
180  * 0	4    8	  12   16   20	 24   28
181  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
182  */
183 
184 #define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
185 #ifdef CONFIG_PHYS_64BIT
186 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
187 #else
188 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
189 #endif
190 
191 #define CONFIG_SYS_BR0_PRELIM \
192 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
193 #define CONFIG_SYS_BR1_PRELIM \
194 	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
195 
196 #define	CONFIG_SYS_OR0_PRELIM		0xff806e65
197 #define	CONFIG_SYS_OR1_PRELIM		0xff806e65
198 
199 #define CONFIG_SYS_FLASH_BANKS_LIST \
200 	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
201 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
202 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
203 #undef	CONFIG_SYS_FLASH_CHECKSUM
204 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
206 
207 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
208 
209 #define CONFIG_FLASH_CFI_DRIVER
210 #define CONFIG_SYS_FLASH_CFI
211 #define CONFIG_SYS_FLASH_EMPTY_INFO
212 
213 #define CONFIG_HWCONFIG			/* enable hwconfig */
214 
215 /*
216  * SDRAM on the Local Bus
217  */
218 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
219 #ifdef CONFIG_PHYS_64BIT
220 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
221 #else
222 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
223 #endif
224 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
225 
226 /*
227  * Base Register 2 and Option Register 2 configure SDRAM.
228  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
229  *
230  * For BR2, need:
231  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
232  *    port-size = 32-bits = BR2[19:20] = 11
233  *    no parity checking = BR2[21:22] = 00
234  *    SDRAM for MSEL = BR2[24:26] = 011
235  *    Valid = BR[31] = 1
236  *
237  * 0	4    8	  12   16   20	 24   28
238  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
239  *
240  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
241  * FIXME: the top 17 bits of BR2.
242  */
243 
244 #define CONFIG_SYS_BR2_PRELIM \
245 	(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
246 	| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
247 
248 /*
249  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
250  *
251  * For OR2, need:
252  *    64MB mask for AM, OR2[0:7] = 1111 1100
253  *		   XAM, OR2[17:18] = 11
254  *    9 columns OR2[19-21] = 010
255  *    13 rows	OR2[23-25] = 100
256  *    EAD set for extra time OR[31] = 1
257  *
258  * 0	4    8	  12   16   20	 24   28
259  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
260  */
261 
262 #define CONFIG_SYS_OR2_PRELIM		0xfc006901
263 
264 #define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
265 #define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
266 #define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
267 #define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
268 
269 /*
270  * Common settings for all Local Bus SDRAM commands.
271  * At run time, either BSMA1516 (for CPU 1.1)
272  *		    or BSMA1617 (for CPU 1.0) (old)
273  * is OR'ed in too.
274  */
275 #define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
276 				| LSDMR_PRETOACT7	\
277 				| LSDMR_ACTTORW7	\
278 				| LSDMR_BL8		\
279 				| LSDMR_WRC4		\
280 				| LSDMR_CL3		\
281 				| LSDMR_RFEN		\
282 				)
283 
284 /*
285  * The CADMUS registers are connected to CS3 on CDS.
286  * The new memory map places CADMUS at 0xf8000000.
287  *
288  * For BR3, need:
289  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
290  *    port-size = 8-bits  = BR[19:20] = 01
291  *    no parity checking  = BR[21:22] = 00
292  *    GPMC for MSEL	  = BR[24:26] = 000
293  *    Valid		  = BR[31]    = 1
294  *
295  * 0	4    8	  12   16   20	 24   28
296  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
297  *
298  * For OR3, need:
299  *    1 MB mask for AM,	  OR[0:16]  = 1111 1111 1111 0000 0
300  *    disable buffer ctrl OR[19]    = 0
301  *    CSNT		  OR[20]    = 1
302  *    ACS		  OR[21:22] = 11
303  *    XACS		  OR[23]    = 1
304  *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
305  *    SETA		  OR[28]    = 0
306  *    TRLX		  OR[29]    = 1
307  *    EHTR		  OR[30]    = 1
308  *    EAD extra time	  OR[31]    = 1
309  *
310  * 0	4    8	  12   16   20	 24   28
311  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
312  */
313 
314 #define CONFIG_FSL_CADMUS
315 
316 #define CADMUS_BASE_ADDR 0xf8000000
317 #ifdef CONFIG_PHYS_64BIT
318 #define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
319 #else
320 #define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
321 #endif
322 #define CONFIG_SYS_BR3_PRELIM \
323 	(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
324 #define CONFIG_SYS_OR3_PRELIM	 0xfff00ff7
325 
326 #define CONFIG_SYS_INIT_RAM_LOCK	1
327 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
328 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
329 
330 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
331 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
332 
333 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
334 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
335 
336 /* Serial Port */
337 #define CONFIG_CONS_INDEX	2
338 #define CONFIG_SYS_NS16550
339 #define CONFIG_SYS_NS16550_SERIAL
340 #define CONFIG_SYS_NS16550_REG_SIZE	1
341 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
342 
343 #define CONFIG_SYS_BAUDRATE_TABLE \
344 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
345 
346 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
347 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
348 
349 /* Use the HUSH parser */
350 #define CONFIG_SYS_HUSH_PARSER
351 
352 /* pass open firmware flat tree */
353 #define CONFIG_OF_LIBFDT		1
354 #define CONFIG_OF_BOARD_SETUP		1
355 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
356 
357 /*
358  * I2C
359  */
360 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
361 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
362 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
363 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
364 #define CONFIG_SYS_I2C_SLAVE		0x7F
365 #define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
366 #define CONFIG_SYS_I2C_OFFSET		0x3000
367 
368 /* EEPROM */
369 #define CONFIG_ID_EEPROM
370 #define CONFIG_SYS_I2C_EEPROM_CCID
371 #define CONFIG_SYS_ID_EEPROM
372 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
373 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
374 
375 /*
376  * General PCI
377  * Memory space is mapped 1-1, but I/O space must start from 0.
378  */
379 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
380 #ifdef CONFIG_PHYS_64BIT
381 #define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
382 #define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
383 #else
384 #define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
385 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
386 #endif
387 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
388 #define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
389 #define CONFIG_SYS_PCI1_IO_BUS	0x00000000
390 #ifdef CONFIG_PHYS_64BIT
391 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
392 #else
393 #define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
394 #endif
395 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
396 
397 #ifdef CONFIG_PCIE1
398 #define CONFIG_SYS_PCIE1_NAME		"Slot"
399 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
400 #ifdef CONFIG_PHYS_64BIT
401 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
402 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
403 #else
404 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
405 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
406 #endif
407 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
408 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
409 #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
410 #ifdef CONFIG_PHYS_64BIT
411 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
412 #else
413 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
414 #endif
415 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
416 #endif
417 
418 /*
419  * RapidIO MMU
420  */
421 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
422 #ifdef CONFIG_PHYS_64BIT
423 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
424 #else
425 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
426 #endif
427 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
428 
429 #ifdef CONFIG_LEGACY
430 #define BRIDGE_ID 17
431 #define VIA_ID 2
432 #else
433 #define BRIDGE_ID 28
434 #define VIA_ID 4
435 #endif
436 
437 #if defined(CONFIG_PCI)
438 
439 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
440 
441 #undef CONFIG_EEPRO100
442 #undef CONFIG_TULIP
443 #define CONFIG_E1000			/* Define e1000 pci Ethernet card */
444 
445 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
446 
447 #endif	/* CONFIG_PCI */
448 
449 
450 #if defined(CONFIG_TSEC_ENET)
451 
452 #define CONFIG_MII		1	/* MII PHY management */
453 #define CONFIG_TSEC1	1
454 #define CONFIG_TSEC1_NAME	"eTSEC0"
455 #define CONFIG_TSEC2	1
456 #define CONFIG_TSEC2_NAME	"eTSEC1"
457 #define CONFIG_TSEC3	1
458 #define CONFIG_TSEC3_NAME	"eTSEC2"
459 #define CONFIG_TSEC4
460 #define CONFIG_TSEC4_NAME	"eTSEC3"
461 #undef CONFIG_MPC85XX_FEC
462 
463 #define CONFIG_PHY_MARVELL
464 
465 #define TSEC1_PHY_ADDR		0
466 #define TSEC2_PHY_ADDR		1
467 #define TSEC3_PHY_ADDR		2
468 #define TSEC4_PHY_ADDR		3
469 
470 #define TSEC1_PHYIDX		0
471 #define TSEC2_PHYIDX		0
472 #define TSEC3_PHYIDX		0
473 #define TSEC4_PHYIDX		0
474 #define TSEC1_FLAGS		TSEC_GIGABIT
475 #define TSEC2_FLAGS		TSEC_GIGABIT
476 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
477 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
478 
479 /* Options are: eTSEC[0-3] */
480 #define CONFIG_ETHPRIME		"eTSEC0"
481 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
482 #endif	/* CONFIG_TSEC_ENET */
483 
484 /*
485  * Environment
486  */
487 #define CONFIG_ENV_IS_IN_FLASH	1
488 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
489 #define CONFIG_ENV_ADDR	0xfff80000
490 #else
491 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
492 #endif
493 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K for env */
494 #define CONFIG_ENV_SIZE		0x2000
495 
496 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
497 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
498 
499 /*
500  * BOOTP options
501  */
502 #define CONFIG_BOOTP_BOOTFILESIZE
503 #define CONFIG_BOOTP_BOOTPATH
504 #define CONFIG_BOOTP_GATEWAY
505 #define CONFIG_BOOTP_HOSTNAME
506 
507 
508 /*
509  * Command line configuration.
510  */
511 #include <config_cmd_default.h>
512 
513 #define CONFIG_CMD_PING
514 #define CONFIG_CMD_I2C
515 #define CONFIG_CMD_MII
516 #define CONFIG_CMD_ELF
517 #define CONFIG_CMD_IRQ
518 #define CONFIG_CMD_SETEXPR
519 #define CONFIG_CMD_REGINFO
520 
521 #if defined(CONFIG_PCI)
522     #define CONFIG_CMD_PCI
523 #endif
524 
525 
526 #undef CONFIG_WATCHDOG			/* watchdog disabled */
527 
528 /*
529  * Miscellaneous configurable options
530  */
531 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
532 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
533 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
534 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
535 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
536 #if defined(CONFIG_CMD_KGDB)
537 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
538 #else
539 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
540 #endif
541 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
542 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
543 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
544 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
545 
546 /*
547  * For booting Linux, the board info and command line data
548  * have to be in the first 64 MB of memory, since this is
549  * the maximum mapped by the Linux kernel during initialization.
550  */
551 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
552 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
553 
554 #if defined(CONFIG_CMD_KGDB)
555 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
556 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
557 #endif
558 
559 /*
560  * Environment Configuration
561  */
562 
563 /* The mac addresses for all ethernet interface */
564 #if defined(CONFIG_TSEC_ENET)
565 #define CONFIG_HAS_ETH0
566 #define CONFIG_ETHADDR	 00:E0:0C:00:00:FD
567 #define CONFIG_HAS_ETH1
568 #define CONFIG_ETH1ADDR	 00:E0:0C:00:01:FD
569 #define CONFIG_HAS_ETH2
570 #define CONFIG_ETH2ADDR	 00:E0:0C:00:02:FD
571 #define CONFIG_HAS_ETH3
572 #define CONFIG_ETH3ADDR	 00:E0:0C:00:03:FD
573 #endif
574 
575 #define CONFIG_IPADDR	 192.168.1.253
576 
577 #define CONFIG_HOSTNAME	 unknown
578 #define CONFIG_ROOTPATH	 "/nfsroot"
579 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
580 #define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */
581 
582 #define CONFIG_SERVERIP	 192.168.1.1
583 #define CONFIG_GATEWAYIP 192.168.1.1
584 #define CONFIG_NETMASK	 255.255.255.0
585 
586 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
587 
588 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
589 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
590 
591 #define CONFIG_BAUDRATE	115200
592 
593 #define	CONFIG_EXTRA_ENV_SETTINGS		\
594 	"hwconfig=fsl_ddr:ecc=off\0"		\
595 	"netdev=eth0\0"				\
596 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
597 	"tftpflash=tftpboot $loadaddr $uboot; "	\
598 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
599 			" +$filesize; "	\
600 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
601 			" +$filesize; "	\
602 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
603 			" $filesize; "	\
604 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
605 			" +$filesize; "	\
606 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
607 			" $filesize\0"	\
608 	"consoledev=ttyS1\0"			\
609 	"ramdiskaddr=2000000\0"			\
610 	"ramdiskfile=ramdisk.uboot\0"		\
611 	"fdtaddr=c00000\0"			\
612 	"fdtfile=mpc8548cds.dtb\0"
613 
614 #define CONFIG_NFSBOOTCOMMAND						\
615    "setenv bootargs root=/dev/nfs rw "					\
616       "nfsroot=$serverip:$rootpath "					\
617       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
618       "console=$consoledev,$baudrate $othbootargs;"			\
619    "tftp $loadaddr $bootfile;"						\
620    "tftp $fdtaddr $fdtfile;"						\
621    "bootm $loadaddr - $fdtaddr"
622 
623 
624 #define CONFIG_RAMBOOTCOMMAND \
625    "setenv bootargs root=/dev/ram rw "					\
626       "console=$consoledev,$baudrate $othbootargs;"			\
627    "tftp $ramdiskaddr $ramdiskfile;"					\
628    "tftp $loadaddr $bootfile;"						\
629    "tftp $fdtaddr $fdtfile;"						\
630    "bootm $loadaddr $ramdiskaddr $fdtaddr"
631 
632 #define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND
633 
634 #endif	/* __CONFIG_H */
635