1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 /* High Level Configuration Options */ 21 #define CONFIG_BOOKE 1 /* BOOKE */ 22 #define CONFIG_E500 1 /* BOOKE e500 family */ 23 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 24 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 25 26 #ifndef CONFIG_SYS_TEXT_BASE 27 #define CONFIG_SYS_TEXT_BASE 0xfff80000 28 #endif 29 30 #define CONFIG_SYS_SRIO 31 #define CONFIG_SRIO1 /* SRIO port 1 */ 32 33 #define CONFIG_PCI /* enable any pci type devices */ 34 #define CONFIG_PCI1 /* PCI controller 1 */ 35 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 36 #undef CONFIG_PCI2 37 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 38 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 39 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 41 42 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 43 #define CONFIG_ENV_OVERWRITE 44 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_FSL_VIA 48 49 #ifndef __ASSEMBLY__ 50 extern unsigned long get_clock_freq(void); 51 #endif 52 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 53 54 /* 55 * These can be toggled for performance analysis, otherwise use default. 56 */ 57 #define CONFIG_L2_CACHE /* toggle L2 cache */ 58 #define CONFIG_BTB /* toggle branch predition */ 59 60 /* 61 * Only possible on E500 Version 2 or newer cores. 62 */ 63 #define CONFIG_ENABLE_36BIT_PHYS 1 64 65 #ifdef CONFIG_PHYS_64BIT 66 #define CONFIG_ADDR_MAP 67 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 68 #endif 69 70 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 71 #define CONFIG_SYS_MEMTEST_END 0x00400000 72 73 #define CONFIG_SYS_CCSRBAR 0xe0000000 74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 75 76 /* DDR Setup */ 77 #define CONFIG_SYS_FSL_DDR2 78 #undef CONFIG_FSL_DDR_INTERACTIVE 79 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 80 #define CONFIG_DDR_SPD 81 82 #define CONFIG_DDR_ECC 83 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 84 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 85 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_NUM_DDR_CONTROLLERS 1 90 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 91 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 92 93 /* I2C addresses of SPD EEPROMs */ 94 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 95 96 /* Make sure required options are set */ 97 #ifndef CONFIG_SPD_EEPROM 98 #error ("CONFIG_SPD_EEPROM is required") 99 #endif 100 101 #undef CONFIG_CLOCKS_IN_MHZ 102 /* 103 * Physical Address Map 104 * 105 * 32bit: 106 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 107 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 108 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 109 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 110 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 111 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 112 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 113 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 114 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 115 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 116 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 117 * 118 * 36bit: 119 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 120 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 121 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 122 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 123 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 124 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 125 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 126 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 127 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 128 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 129 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 130 * 131 */ 132 133 134 /* 135 * Local Bus Definitions 136 */ 137 138 /* 139 * FLASH on the Local Bus 140 * Two banks, 8M each, using the CFI driver. 141 * Boot from BR0/OR0 bank at 0xff00_0000 142 * Alternate BR1/OR1 bank at 0xff80_0000 143 * 144 * BR0, BR1: 145 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 146 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 147 * Port Size = 16 bits = BRx[19:20] = 10 148 * Use GPCM = BRx[24:26] = 000 149 * Valid = BRx[31] = 1 150 * 151 * 0 4 8 12 16 20 24 28 152 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 153 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 154 * 155 * OR0, OR1: 156 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 157 * Reserved ORx[17:18] = 11, confusion here? 158 * CSNT = ORx[20] = 1 159 * ACS = half cycle delay = ORx[21:22] = 11 160 * SCY = 6 = ORx[24:27] = 0110 161 * TRLX = use relaxed timing = ORx[29] = 1 162 * EAD = use external address latch delay = OR[31] = 1 163 * 164 * 0 4 8 12 16 20 24 28 165 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 166 */ 167 168 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 169 #ifdef CONFIG_PHYS_64BIT 170 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 171 #else 172 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 173 #endif 174 175 #define CONFIG_SYS_BR0_PRELIM \ 176 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 177 #define CONFIG_SYS_BR1_PRELIM \ 178 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 179 180 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 181 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 182 183 #define CONFIG_SYS_FLASH_BANKS_LIST \ 184 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 185 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 186 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 197 #define CONFIG_HWCONFIG /* enable hwconfig */ 198 199 /* 200 * SDRAM on the Local Bus 201 */ 202 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 203 #ifdef CONFIG_PHYS_64BIT 204 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 205 #else 206 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 207 #endif 208 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 209 210 /* 211 * Base Register 2 and Option Register 2 configure SDRAM. 212 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 213 * 214 * For BR2, need: 215 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 216 * port-size = 32-bits = BR2[19:20] = 11 217 * no parity checking = BR2[21:22] = 00 218 * SDRAM for MSEL = BR2[24:26] = 011 219 * Valid = BR[31] = 1 220 * 221 * 0 4 8 12 16 20 24 28 222 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 223 * 224 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 225 * FIXME: the top 17 bits of BR2. 226 */ 227 228 #define CONFIG_SYS_BR2_PRELIM \ 229 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 230 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 231 232 /* 233 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 234 * 235 * For OR2, need: 236 * 64MB mask for AM, OR2[0:7] = 1111 1100 237 * XAM, OR2[17:18] = 11 238 * 9 columns OR2[19-21] = 010 239 * 13 rows OR2[23-25] = 100 240 * EAD set for extra time OR[31] = 1 241 * 242 * 0 4 8 12 16 20 24 28 243 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 244 */ 245 246 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 247 248 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 249 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 250 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 251 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 252 253 /* 254 * Common settings for all Local Bus SDRAM commands. 255 * At run time, either BSMA1516 (for CPU 1.1) 256 * or BSMA1617 (for CPU 1.0) (old) 257 * is OR'ed in too. 258 */ 259 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 260 | LSDMR_PRETOACT7 \ 261 | LSDMR_ACTTORW7 \ 262 | LSDMR_BL8 \ 263 | LSDMR_WRC4 \ 264 | LSDMR_CL3 \ 265 | LSDMR_RFEN \ 266 ) 267 268 /* 269 * The CADMUS registers are connected to CS3 on CDS. 270 * The new memory map places CADMUS at 0xf8000000. 271 * 272 * For BR3, need: 273 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 274 * port-size = 8-bits = BR[19:20] = 01 275 * no parity checking = BR[21:22] = 00 276 * GPMC for MSEL = BR[24:26] = 000 277 * Valid = BR[31] = 1 278 * 279 * 0 4 8 12 16 20 24 28 280 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 281 * 282 * For OR3, need: 283 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 284 * disable buffer ctrl OR[19] = 0 285 * CSNT OR[20] = 1 286 * ACS OR[21:22] = 11 287 * XACS OR[23] = 1 288 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 289 * SETA OR[28] = 0 290 * TRLX OR[29] = 1 291 * EHTR OR[30] = 1 292 * EAD extra time OR[31] = 1 293 * 294 * 0 4 8 12 16 20 24 28 295 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 296 */ 297 298 #define CONFIG_FSL_CADMUS 299 300 #define CADMUS_BASE_ADDR 0xf8000000 301 #ifdef CONFIG_PHYS_64BIT 302 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 303 #else 304 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 305 #endif 306 #define CONFIG_SYS_BR3_PRELIM \ 307 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 308 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 309 310 #define CONFIG_SYS_INIT_RAM_LOCK 1 311 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 312 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 313 314 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 315 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 316 317 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 318 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 319 320 /* Serial Port */ 321 #define CONFIG_CONS_INDEX 2 322 #define CONFIG_SYS_NS16550 323 #define CONFIG_SYS_NS16550_SERIAL 324 #define CONFIG_SYS_NS16550_REG_SIZE 1 325 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 326 327 #define CONFIG_SYS_BAUDRATE_TABLE \ 328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 329 330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 332 333 /* Use the HUSH parser */ 334 #define CONFIG_SYS_HUSH_PARSER 335 336 /* pass open firmware flat tree */ 337 #define CONFIG_OF_LIBFDT 1 338 #define CONFIG_OF_BOARD_SETUP 1 339 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 340 341 /* 342 * I2C 343 */ 344 #define CONFIG_SYS_I2C 345 #define CONFIG_SYS_I2C_FSL 346 #define CONFIG_SYS_FSL_I2C_SPEED 400000 347 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 348 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 349 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 350 351 /* EEPROM */ 352 #define CONFIG_ID_EEPROM 353 #define CONFIG_SYS_I2C_EEPROM_CCID 354 #define CONFIG_SYS_ID_EEPROM 355 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 356 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 357 358 /* 359 * General PCI 360 * Memory space is mapped 1-1, but I/O space must start from 0. 361 */ 362 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 365 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 366 #else 367 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 368 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 369 #endif 370 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 371 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 372 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 373 #ifdef CONFIG_PHYS_64BIT 374 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 375 #else 376 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 377 #endif 378 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 379 380 #ifdef CONFIG_PCIE1 381 #define CONFIG_SYS_PCIE1_NAME "Slot" 382 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 383 #ifdef CONFIG_PHYS_64BIT 384 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 385 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 386 #else 387 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 388 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 389 #endif 390 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 391 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 392 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 393 #ifdef CONFIG_PHYS_64BIT 394 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 395 #else 396 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 397 #endif 398 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 399 #endif 400 401 /* 402 * RapidIO MMU 403 */ 404 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 407 #else 408 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 409 #endif 410 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 411 412 #ifdef CONFIG_LEGACY 413 #define BRIDGE_ID 17 414 #define VIA_ID 2 415 #else 416 #define BRIDGE_ID 28 417 #define VIA_ID 4 418 #endif 419 420 #if defined(CONFIG_PCI) 421 422 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 423 424 #undef CONFIG_EEPRO100 425 #undef CONFIG_TULIP 426 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 427 428 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 429 430 #endif /* CONFIG_PCI */ 431 432 433 #if defined(CONFIG_TSEC_ENET) 434 435 #define CONFIG_MII 1 /* MII PHY management */ 436 #define CONFIG_TSEC1 1 437 #define CONFIG_TSEC1_NAME "eTSEC0" 438 #define CONFIG_TSEC2 1 439 #define CONFIG_TSEC2_NAME "eTSEC1" 440 #define CONFIG_TSEC3 1 441 #define CONFIG_TSEC3_NAME "eTSEC2" 442 #define CONFIG_TSEC4 443 #define CONFIG_TSEC4_NAME "eTSEC3" 444 #undef CONFIG_MPC85XX_FEC 445 446 #define CONFIG_PHY_MARVELL 447 448 #define TSEC1_PHY_ADDR 0 449 #define TSEC2_PHY_ADDR 1 450 #define TSEC3_PHY_ADDR 2 451 #define TSEC4_PHY_ADDR 3 452 453 #define TSEC1_PHYIDX 0 454 #define TSEC2_PHYIDX 0 455 #define TSEC3_PHYIDX 0 456 #define TSEC4_PHYIDX 0 457 #define TSEC1_FLAGS TSEC_GIGABIT 458 #define TSEC2_FLAGS TSEC_GIGABIT 459 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 460 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 461 462 /* Options are: eTSEC[0-3] */ 463 #define CONFIG_ETHPRIME "eTSEC0" 464 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 465 #endif /* CONFIG_TSEC_ENET */ 466 467 /* 468 * Environment 469 */ 470 #define CONFIG_ENV_IS_IN_FLASH 1 471 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 472 #define CONFIG_ENV_ADDR 0xfff80000 473 #else 474 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 475 #endif 476 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 477 #define CONFIG_ENV_SIZE 0x2000 478 479 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 480 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 481 482 /* 483 * BOOTP options 484 */ 485 #define CONFIG_BOOTP_BOOTFILESIZE 486 #define CONFIG_BOOTP_BOOTPATH 487 #define CONFIG_BOOTP_GATEWAY 488 #define CONFIG_BOOTP_HOSTNAME 489 490 491 /* 492 * Command line configuration. 493 */ 494 #include <config_cmd_default.h> 495 496 #define CONFIG_CMD_PING 497 #define CONFIG_CMD_I2C 498 #define CONFIG_CMD_MII 499 #define CONFIG_CMD_ELF 500 #define CONFIG_CMD_IRQ 501 #define CONFIG_CMD_SETEXPR 502 #define CONFIG_CMD_REGINFO 503 504 #if defined(CONFIG_PCI) 505 #define CONFIG_CMD_PCI 506 #endif 507 508 509 #undef CONFIG_WATCHDOG /* watchdog disabled */ 510 511 /* 512 * Miscellaneous configurable options 513 */ 514 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 515 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 516 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 517 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 518 #if defined(CONFIG_CMD_KGDB) 519 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 520 #else 521 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 522 #endif 523 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 524 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 525 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 526 527 /* 528 * For booting Linux, the board info and command line data 529 * have to be in the first 64 MB of memory, since this is 530 * the maximum mapped by the Linux kernel during initialization. 531 */ 532 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 533 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 534 535 #if defined(CONFIG_CMD_KGDB) 536 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 537 #endif 538 539 /* 540 * Environment Configuration 541 */ 542 543 /* The mac addresses for all ethernet interface */ 544 #if defined(CONFIG_TSEC_ENET) 545 #define CONFIG_HAS_ETH0 546 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 547 #define CONFIG_HAS_ETH1 548 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 549 #define CONFIG_HAS_ETH2 550 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 551 #define CONFIG_HAS_ETH3 552 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 553 #endif 554 555 #define CONFIG_IPADDR 192.168.1.253 556 557 #define CONFIG_HOSTNAME unknown 558 #define CONFIG_ROOTPATH "/nfsroot" 559 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 560 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 561 562 #define CONFIG_SERVERIP 192.168.1.1 563 #define CONFIG_GATEWAYIP 192.168.1.1 564 #define CONFIG_NETMASK 255.255.255.0 565 566 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 567 568 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 569 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 570 571 #define CONFIG_BAUDRATE 115200 572 573 #define CONFIG_EXTRA_ENV_SETTINGS \ 574 "hwconfig=fsl_ddr:ecc=off\0" \ 575 "netdev=eth0\0" \ 576 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 577 "tftpflash=tftpboot $loadaddr $uboot; " \ 578 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 579 " +$filesize; " \ 580 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 581 " +$filesize; " \ 582 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 583 " $filesize; " \ 584 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 585 " +$filesize; " \ 586 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 587 " $filesize\0" \ 588 "consoledev=ttyS1\0" \ 589 "ramdiskaddr=2000000\0" \ 590 "ramdiskfile=ramdisk.uboot\0" \ 591 "fdtaddr=c00000\0" \ 592 "fdtfile=mpc8548cds.dtb\0" 593 594 #define CONFIG_NFSBOOTCOMMAND \ 595 "setenv bootargs root=/dev/nfs rw " \ 596 "nfsroot=$serverip:$rootpath " \ 597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 598 "console=$consoledev,$baudrate $othbootargs;" \ 599 "tftp $loadaddr $bootfile;" \ 600 "tftp $fdtaddr $fdtfile;" \ 601 "bootm $loadaddr - $fdtaddr" 602 603 604 #define CONFIG_RAMBOOTCOMMAND \ 605 "setenv bootargs root=/dev/ram rw " \ 606 "console=$consoledev,$baudrate $othbootargs;" \ 607 "tftp $ramdiskaddr $ramdiskfile;" \ 608 "tftp $loadaddr $bootfile;" \ 609 "tftp $fdtaddr $fdtfile;" \ 610 "bootm $loadaddr $ramdiskaddr $fdtaddr" 611 612 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 613 614 #endif /* __CONFIG_H */ 615