1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8548cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_SYS_SRIO 16 #define CONFIG_SRIO1 /* SRIO port 1 */ 17 18 #define CONFIG_PCI1 /* PCI controller 1 */ 19 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 20 #undef CONFIG_PCI2 21 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 23 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 25 26 #define CONFIG_ENV_OVERWRITE 27 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 28 29 #define CONFIG_FSL_VIA 30 31 #ifndef __ASSEMBLY__ 32 extern unsigned long get_clock_freq(void); 33 #endif 34 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 35 36 /* 37 * These can be toggled for performance analysis, otherwise use default. 38 */ 39 #define CONFIG_L2_CACHE /* toggle L2 cache */ 40 #define CONFIG_BTB /* toggle branch predition */ 41 42 /* 43 * Only possible on E500 Version 2 or newer cores. 44 */ 45 #define CONFIG_ENABLE_36BIT_PHYS 1 46 47 #ifdef CONFIG_PHYS_64BIT 48 #define CONFIG_ADDR_MAP 49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 50 #endif 51 52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 53 #define CONFIG_SYS_MEMTEST_END 0x00400000 54 55 #define CONFIG_SYS_CCSRBAR 0xe0000000 56 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 57 58 /* DDR Setup */ 59 #undef CONFIG_FSL_DDR_INTERACTIVE 60 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 61 #define CONFIG_DDR_SPD 62 63 #define CONFIG_DDR_ECC 64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 65 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 66 67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 69 70 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 71 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 72 73 /* I2C addresses of SPD EEPROMs */ 74 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 75 76 /* Make sure required options are set */ 77 #ifndef CONFIG_SPD_EEPROM 78 #error ("CONFIG_SPD_EEPROM is required") 79 #endif 80 81 #undef CONFIG_CLOCKS_IN_MHZ 82 /* 83 * Physical Address Map 84 * 85 * 32bit: 86 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 87 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 88 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 89 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 90 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 91 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 92 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 93 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 94 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 95 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 96 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 97 * 98 * 36bit: 99 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 100 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 101 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 102 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 103 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 104 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 105 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 106 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 107 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 108 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 109 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 110 * 111 */ 112 113 /* 114 * Local Bus Definitions 115 */ 116 117 /* 118 * FLASH on the Local Bus 119 * Two banks, 8M each, using the CFI driver. 120 * Boot from BR0/OR0 bank at 0xff00_0000 121 * Alternate BR1/OR1 bank at 0xff80_0000 122 * 123 * BR0, BR1: 124 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 125 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 126 * Port Size = 16 bits = BRx[19:20] = 10 127 * Use GPCM = BRx[24:26] = 000 128 * Valid = BRx[31] = 1 129 * 130 * 0 4 8 12 16 20 24 28 131 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 132 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 133 * 134 * OR0, OR1: 135 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 136 * Reserved ORx[17:18] = 11, confusion here? 137 * CSNT = ORx[20] = 1 138 * ACS = half cycle delay = ORx[21:22] = 11 139 * SCY = 6 = ORx[24:27] = 0110 140 * TRLX = use relaxed timing = ORx[29] = 1 141 * EAD = use external address latch delay = OR[31] = 1 142 * 143 * 0 4 8 12 16 20 24 28 144 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 145 */ 146 147 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 150 #else 151 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 152 #endif 153 154 #define CONFIG_SYS_BR0_PRELIM \ 155 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 156 #define CONFIG_SYS_BR1_PRELIM \ 157 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 158 159 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 160 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 161 162 #define CONFIG_SYS_FLASH_BANKS_LIST \ 163 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 164 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 165 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 166 #undef CONFIG_SYS_FLASH_CHECKSUM 167 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 168 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 169 170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 171 172 #define CONFIG_SYS_FLASH_EMPTY_INFO 173 174 #define CONFIG_HWCONFIG /* enable hwconfig */ 175 176 /* 177 * SDRAM on the Local Bus 178 */ 179 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 180 #ifdef CONFIG_PHYS_64BIT 181 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 182 #else 183 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 184 #endif 185 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 186 187 /* 188 * Base Register 2 and Option Register 2 configure SDRAM. 189 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 190 * 191 * For BR2, need: 192 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 193 * port-size = 32-bits = BR2[19:20] = 11 194 * no parity checking = BR2[21:22] = 00 195 * SDRAM for MSEL = BR2[24:26] = 011 196 * Valid = BR[31] = 1 197 * 198 * 0 4 8 12 16 20 24 28 199 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 200 * 201 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 202 * FIXME: the top 17 bits of BR2. 203 */ 204 205 #define CONFIG_SYS_BR2_PRELIM \ 206 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 207 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 208 209 /* 210 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 211 * 212 * For OR2, need: 213 * 64MB mask for AM, OR2[0:7] = 1111 1100 214 * XAM, OR2[17:18] = 11 215 * 9 columns OR2[19-21] = 010 216 * 13 rows OR2[23-25] = 100 217 * EAD set for extra time OR[31] = 1 218 * 219 * 0 4 8 12 16 20 24 28 220 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 221 */ 222 223 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 224 225 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 226 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 227 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 228 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 229 230 /* 231 * Common settings for all Local Bus SDRAM commands. 232 * At run time, either BSMA1516 (for CPU 1.1) 233 * or BSMA1617 (for CPU 1.0) (old) 234 * is OR'ed in too. 235 */ 236 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 237 | LSDMR_PRETOACT7 \ 238 | LSDMR_ACTTORW7 \ 239 | LSDMR_BL8 \ 240 | LSDMR_WRC4 \ 241 | LSDMR_CL3 \ 242 | LSDMR_RFEN \ 243 ) 244 245 /* 246 * The CADMUS registers are connected to CS3 on CDS. 247 * The new memory map places CADMUS at 0xf8000000. 248 * 249 * For BR3, need: 250 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 251 * port-size = 8-bits = BR[19:20] = 01 252 * no parity checking = BR[21:22] = 00 253 * GPMC for MSEL = BR[24:26] = 000 254 * Valid = BR[31] = 1 255 * 256 * 0 4 8 12 16 20 24 28 257 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 258 * 259 * For OR3, need: 260 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 261 * disable buffer ctrl OR[19] = 0 262 * CSNT OR[20] = 1 263 * ACS OR[21:22] = 11 264 * XACS OR[23] = 1 265 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 266 * SETA OR[28] = 0 267 * TRLX OR[29] = 1 268 * EHTR OR[30] = 1 269 * EAD extra time OR[31] = 1 270 * 271 * 0 4 8 12 16 20 24 28 272 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 273 */ 274 275 #define CONFIG_FSL_CADMUS 276 277 #define CADMUS_BASE_ADDR 0xf8000000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 280 #else 281 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 282 #endif 283 #define CONFIG_SYS_BR3_PRELIM \ 284 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 285 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 286 287 #define CONFIG_SYS_INIT_RAM_LOCK 1 288 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 289 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 290 291 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 292 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 293 294 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 295 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 296 297 /* Serial Port */ 298 #define CONFIG_SYS_NS16550_SERIAL 299 #define CONFIG_SYS_NS16550_REG_SIZE 1 300 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 301 302 #define CONFIG_SYS_BAUDRATE_TABLE \ 303 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 304 305 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 306 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 307 308 /* 309 * I2C 310 */ 311 #define CONFIG_SYS_I2C 312 #define CONFIG_SYS_I2C_FSL 313 #define CONFIG_SYS_FSL_I2C_SPEED 400000 314 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 315 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 316 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 317 318 /* EEPROM */ 319 #define CONFIG_ID_EEPROM 320 #define CONFIG_SYS_I2C_EEPROM_CCID 321 #define CONFIG_SYS_ID_EEPROM 322 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 324 325 /* 326 * General PCI 327 * Memory space is mapped 1-1, but I/O space must start from 0. 328 */ 329 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 330 #ifdef CONFIG_PHYS_64BIT 331 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 332 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 333 #else 334 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 335 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 336 #endif 337 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 338 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 339 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 340 #ifdef CONFIG_PHYS_64BIT 341 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 342 #else 343 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 344 #endif 345 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 346 347 #ifdef CONFIG_PCIE1 348 #define CONFIG_SYS_PCIE1_NAME "Slot" 349 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 350 #ifdef CONFIG_PHYS_64BIT 351 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 352 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 353 #else 354 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 355 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 356 #endif 357 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 358 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 359 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 360 #ifdef CONFIG_PHYS_64BIT 361 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 362 #else 363 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 364 #endif 365 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 366 #endif 367 368 /* 369 * RapidIO MMU 370 */ 371 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 372 #ifdef CONFIG_PHYS_64BIT 373 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 374 #else 375 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 376 #endif 377 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 378 379 #ifdef CONFIG_LEGACY 380 #define BRIDGE_ID 17 381 #define VIA_ID 2 382 #else 383 #define BRIDGE_ID 28 384 #define VIA_ID 4 385 #endif 386 387 #if defined(CONFIG_PCI) 388 #undef CONFIG_EEPRO100 389 #undef CONFIG_TULIP 390 391 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 392 393 #endif /* CONFIG_PCI */ 394 395 #if defined(CONFIG_TSEC_ENET) 396 397 #define CONFIG_TSEC1 1 398 #define CONFIG_TSEC1_NAME "eTSEC0" 399 #define CONFIG_TSEC2 1 400 #define CONFIG_TSEC2_NAME "eTSEC1" 401 #define CONFIG_TSEC3 1 402 #define CONFIG_TSEC3_NAME "eTSEC2" 403 #define CONFIG_TSEC4 404 #define CONFIG_TSEC4_NAME "eTSEC3" 405 #undef CONFIG_MPC85XX_FEC 406 407 #define TSEC1_PHY_ADDR 0 408 #define TSEC2_PHY_ADDR 1 409 #define TSEC3_PHY_ADDR 2 410 #define TSEC4_PHY_ADDR 3 411 412 #define TSEC1_PHYIDX 0 413 #define TSEC2_PHYIDX 0 414 #define TSEC3_PHYIDX 0 415 #define TSEC4_PHYIDX 0 416 #define TSEC1_FLAGS TSEC_GIGABIT 417 #define TSEC2_FLAGS TSEC_GIGABIT 418 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 420 421 /* Options are: eTSEC[0-3] */ 422 #define CONFIG_ETHPRIME "eTSEC0" 423 #endif /* CONFIG_TSEC_ENET */ 424 425 /* 426 * Environment 427 */ 428 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 429 #define CONFIG_ENV_ADDR 0xfff80000 430 #else 431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 432 #endif 433 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 434 #define CONFIG_ENV_SIZE 0x2000 435 436 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 437 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 438 439 /* 440 * BOOTP options 441 */ 442 #define CONFIG_BOOTP_BOOTFILESIZE 443 444 #undef CONFIG_WATCHDOG /* watchdog disabled */ 445 446 /* 447 * Miscellaneous configurable options 448 */ 449 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 450 451 /* 452 * For booting Linux, the board info and command line data 453 * have to be in the first 64 MB of memory, since this is 454 * the maximum mapped by the Linux kernel during initialization. 455 */ 456 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 457 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 458 459 #if defined(CONFIG_CMD_KGDB) 460 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 461 #endif 462 463 /* 464 * Environment Configuration 465 */ 466 #if defined(CONFIG_TSEC_ENET) 467 #define CONFIG_HAS_ETH0 468 #define CONFIG_HAS_ETH1 469 #define CONFIG_HAS_ETH2 470 #define CONFIG_HAS_ETH3 471 #endif 472 473 #define CONFIG_IPADDR 192.168.1.253 474 475 #define CONFIG_HOSTNAME "unknown" 476 #define CONFIG_ROOTPATH "/nfsroot" 477 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 478 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 479 480 #define CONFIG_SERVERIP 192.168.1.1 481 #define CONFIG_GATEWAYIP 192.168.1.1 482 #define CONFIG_NETMASK 255.255.255.0 483 484 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 485 486 #define CONFIG_EXTRA_ENV_SETTINGS \ 487 "hwconfig=fsl_ddr:ecc=off\0" \ 488 "netdev=eth0\0" \ 489 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 490 "tftpflash=tftpboot $loadaddr $uboot; " \ 491 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 492 " +$filesize; " \ 493 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 494 " +$filesize; " \ 495 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 496 " $filesize; " \ 497 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 498 " +$filesize; " \ 499 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 500 " $filesize\0" \ 501 "consoledev=ttyS1\0" \ 502 "ramdiskaddr=2000000\0" \ 503 "ramdiskfile=ramdisk.uboot\0" \ 504 "fdtaddr=1e00000\0" \ 505 "fdtfile=mpc8548cds.dtb\0" 506 507 #define CONFIG_NFSBOOTCOMMAND \ 508 "setenv bootargs root=/dev/nfs rw " \ 509 "nfsroot=$serverip:$rootpath " \ 510 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 511 "console=$consoledev,$baudrate $othbootargs;" \ 512 "tftp $loadaddr $bootfile;" \ 513 "tftp $fdtaddr $fdtfile;" \ 514 "bootm $loadaddr - $fdtaddr" 515 516 #define CONFIG_RAMBOOTCOMMAND \ 517 "setenv bootargs root=/dev/ram rw " \ 518 "console=$consoledev,$baudrate $othbootargs;" \ 519 "tftp $ramdiskaddr $ramdiskfile;" \ 520 "tftp $loadaddr $bootfile;" \ 521 "tftp $fdtaddr $fdtfile;" \ 522 "bootm $loadaddr $ramdiskaddr $fdtaddr" 523 524 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 525 526 #endif /* __CONFIG_H */ 527