1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xfff80000 41 #endif 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 46 #define CONFIG_PCI /* enable any pci type devices */ 47 #define CONFIG_PCI1 /* PCI controller 1 */ 48 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 49 #undef CONFIG_PCI2 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 58 59 #define CONFIG_FSL_VIA 60 61 #ifndef __ASSEMBLY__ 62 extern unsigned long get_clock_freq(void); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 88 89 /* DDR Setup */ 90 #define CONFIG_FSL_DDR2 91 #undef CONFIG_FSL_DDR_INTERACTIVE 92 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 93 #define CONFIG_DDR_SPD 94 #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ 95 96 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 97 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 98 99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 101 102 #define CONFIG_NUM_DDR_CONTROLLERS 1 103 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 104 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 105 106 /* I2C addresses of SPD EEPROMs */ 107 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 108 109 /* Make sure required options are set */ 110 #ifndef CONFIG_SPD_EEPROM 111 #error ("CONFIG_SPD_EEPROM is required") 112 #endif 113 114 #undef CONFIG_CLOCKS_IN_MHZ 115 116 /* 117 * Local Bus Definitions 118 */ 119 120 /* 121 * FLASH on the Local Bus 122 * Two banks, 8M each, using the CFI driver. 123 * Boot from BR0/OR0 bank at 0xff00_0000 124 * Alternate BR1/OR1 bank at 0xff80_0000 125 * 126 * BR0, BR1: 127 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 128 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 129 * Port Size = 16 bits = BRx[19:20] = 10 130 * Use GPCM = BRx[24:26] = 000 131 * Valid = BRx[31] = 1 132 * 133 * 0 4 8 12 16 20 24 28 134 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 135 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 136 * 137 * OR0, OR1: 138 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 139 * Reserved ORx[17:18] = 11, confusion here? 140 * CSNT = ORx[20] = 1 141 * ACS = half cycle delay = ORx[21:22] = 11 142 * SCY = 6 = ORx[24:27] = 0110 143 * TRLX = use relaxed timing = ORx[29] = 1 144 * EAD = use external address latch delay = OR[31] = 1 145 * 146 * 0 4 8 12 16 20 24 28 147 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 148 */ 149 150 #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ 151 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 152 153 #define CONFIG_SYS_BR0_PRELIM 0xff801001 154 #define CONFIG_SYS_BR1_PRELIM 0xff001001 155 156 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 157 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 158 159 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 160 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 161 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 162 #undef CONFIG_SYS_FLASH_CHECKSUM 163 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 165 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 167 168 #define CONFIG_FLASH_CFI_DRIVER 169 #define CONFIG_SYS_FLASH_CFI 170 #define CONFIG_SYS_FLASH_EMPTY_INFO 171 172 173 /* 174 * SDRAM on the Local Bus 175 */ 176 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 177 #define CONFIG_SYS_LBC_CACHE_SIZE 64 178 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 179 #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 180 181 #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ 182 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 183 184 /* 185 * Base Register 2 and Option Register 2 configure SDRAM. 186 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 187 * 188 * For BR2, need: 189 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 190 * port-size = 32-bits = BR2[19:20] = 11 191 * no parity checking = BR2[21:22] = 00 192 * SDRAM for MSEL = BR2[24:26] = 011 193 * Valid = BR[31] = 1 194 * 195 * 0 4 8 12 16 20 24 28 196 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 197 * 198 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 199 * FIXME: the top 17 bits of BR2. 200 */ 201 202 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 203 204 /* 205 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 206 * 207 * For OR2, need: 208 * 64MB mask for AM, OR2[0:7] = 1111 1100 209 * XAM, OR2[17:18] = 11 210 * 9 columns OR2[19-21] = 010 211 * 13 rows OR2[23-25] = 100 212 * EAD set for extra time OR[31] = 1 213 * 214 * 0 4 8 12 16 20 24 28 215 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 216 */ 217 218 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 219 220 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 221 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 222 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 223 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 224 225 /* 226 * Common settings for all Local Bus SDRAM commands. 227 * At run time, either BSMA1516 (for CPU 1.1) 228 * or BSMA1617 (for CPU 1.0) (old) 229 * is OR'ed in too. 230 */ 231 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 232 | LSDMR_PRETOACT7 \ 233 | LSDMR_ACTTORW7 \ 234 | LSDMR_BL8 \ 235 | LSDMR_WRC4 \ 236 | LSDMR_CL3 \ 237 | LSDMR_RFEN \ 238 ) 239 240 /* 241 * The CADMUS registers are connected to CS3 on CDS. 242 * The new memory map places CADMUS at 0xf8000000. 243 * 244 * For BR3, need: 245 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 246 * port-size = 8-bits = BR[19:20] = 01 247 * no parity checking = BR[21:22] = 00 248 * GPMC for MSEL = BR[24:26] = 000 249 * Valid = BR[31] = 1 250 * 251 * 0 4 8 12 16 20 24 28 252 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 253 * 254 * For OR3, need: 255 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 256 * disable buffer ctrl OR[19] = 0 257 * CSNT OR[20] = 1 258 * ACS OR[21:22] = 11 259 * XACS OR[23] = 1 260 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 261 * SETA OR[28] = 0 262 * TRLX OR[29] = 1 263 * EHTR OR[30] = 1 264 * EAD extra time OR[31] = 1 265 * 266 * 0 4 8 12 16 20 24 28 267 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 268 */ 269 270 #define CONFIG_FSL_CADMUS 271 272 #define CADMUS_BASE_ADDR 0xf8000000 273 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 274 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 275 276 #define CONFIG_SYS_INIT_RAM_LOCK 1 277 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 278 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 279 280 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 281 282 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 283 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 284 285 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 286 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 287 288 /* Serial Port */ 289 #define CONFIG_CONS_INDEX 2 290 #define CONFIG_SYS_NS16550 291 #define CONFIG_SYS_NS16550_SERIAL 292 #define CONFIG_SYS_NS16550_REG_SIZE 1 293 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 294 295 #define CONFIG_SYS_BAUDRATE_TABLE \ 296 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 297 298 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 300 301 /* Use the HUSH parser */ 302 #define CONFIG_SYS_HUSH_PARSER 303 #ifdef CONFIG_SYS_HUSH_PARSER 304 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 305 #endif 306 307 /* pass open firmware flat tree */ 308 #define CONFIG_OF_LIBFDT 1 309 #define CONFIG_OF_BOARD_SETUP 1 310 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 311 312 /* 313 * I2C 314 */ 315 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 316 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 317 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 318 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 319 #define CONFIG_SYS_I2C_SLAVE 0x7F 320 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 321 #define CONFIG_SYS_I2C_OFFSET 0x3000 322 323 /* EEPROM */ 324 #define CONFIG_ID_EEPROM 325 #define CONFIG_SYS_I2C_EEPROM_CCID 326 #define CONFIG_SYS_ID_EEPROM 327 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 328 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 329 330 /* 331 * General PCI 332 * Memory space is mapped 1-1, but I/O space must start from 0. 333 */ 334 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 335 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 336 337 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 338 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 339 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 340 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 341 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 342 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 343 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 344 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 345 346 #ifdef CONFIG_PCI2 347 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 348 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 349 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 350 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 351 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 352 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 353 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 354 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 355 #endif 356 357 #ifdef CONFIG_PCIE1 358 #define CONFIG_SYS_PCIE1_NAME "Slot" 359 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 360 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 361 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 362 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 363 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 364 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 365 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 366 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 367 #endif 368 369 /* 370 * RapidIO MMU 371 */ 372 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 373 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 374 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 375 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 376 377 #ifdef CONFIG_LEGACY 378 #define BRIDGE_ID 17 379 #define VIA_ID 2 380 #else 381 #define BRIDGE_ID 28 382 #define VIA_ID 4 383 #endif 384 385 #if defined(CONFIG_PCI) 386 387 #define CONFIG_NET_MULTI 388 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 389 390 #undef CONFIG_EEPRO100 391 #undef CONFIG_TULIP 392 393 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 394 395 #endif /* CONFIG_PCI */ 396 397 398 #if defined(CONFIG_TSEC_ENET) 399 400 #ifndef CONFIG_NET_MULTI 401 #define CONFIG_NET_MULTI 1 402 #endif 403 404 #define CONFIG_MII 1 /* MII PHY management */ 405 #define CONFIG_TSEC1 1 406 #define CONFIG_TSEC1_NAME "eTSEC0" 407 #define CONFIG_TSEC2 1 408 #define CONFIG_TSEC2_NAME "eTSEC1" 409 #define CONFIG_TSEC3 1 410 #define CONFIG_TSEC3_NAME "eTSEC2" 411 #define CONFIG_TSEC4 412 #define CONFIG_TSEC4_NAME "eTSEC3" 413 #undef CONFIG_MPC85XX_FEC 414 415 #define TSEC1_PHY_ADDR 0 416 #define TSEC2_PHY_ADDR 1 417 #define TSEC3_PHY_ADDR 2 418 #define TSEC4_PHY_ADDR 3 419 420 #define TSEC1_PHYIDX 0 421 #define TSEC2_PHYIDX 0 422 #define TSEC3_PHYIDX 0 423 #define TSEC4_PHYIDX 0 424 #define TSEC1_FLAGS TSEC_GIGABIT 425 #define TSEC2_FLAGS TSEC_GIGABIT 426 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 428 429 /* Options are: eTSEC[0-3] */ 430 #define CONFIG_ETHPRIME "eTSEC0" 431 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 432 #endif /* CONFIG_TSEC_ENET */ 433 434 /* 435 * Environment 436 */ 437 #define CONFIG_ENV_IS_IN_FLASH 1 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 439 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 440 #define CONFIG_ENV_SIZE 0x2000 441 442 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 444 445 /* 446 * BOOTP options 447 */ 448 #define CONFIG_BOOTP_BOOTFILESIZE 449 #define CONFIG_BOOTP_BOOTPATH 450 #define CONFIG_BOOTP_GATEWAY 451 #define CONFIG_BOOTP_HOSTNAME 452 453 454 /* 455 * Command line configuration. 456 */ 457 #include <config_cmd_default.h> 458 459 #define CONFIG_CMD_PING 460 #define CONFIG_CMD_I2C 461 #define CONFIG_CMD_MII 462 #define CONFIG_CMD_ELF 463 #define CONFIG_CMD_IRQ 464 #define CONFIG_CMD_SETEXPR 465 #define CONFIG_CMD_REGINFO 466 467 #if defined(CONFIG_PCI) 468 #define CONFIG_CMD_PCI 469 #endif 470 471 472 #undef CONFIG_WATCHDOG /* watchdog disabled */ 473 474 /* 475 * Miscellaneous configurable options 476 */ 477 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 478 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 479 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 480 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 481 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 482 #if defined(CONFIG_CMD_KGDB) 483 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 484 #else 485 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 486 #endif 487 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 488 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 489 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 490 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 491 492 /* 493 * For booting Linux, the board info and command line data 494 * have to be in the first 16 MB of memory, since this is 495 * the maximum mapped by the Linux kernel during initialization. 496 */ 497 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 498 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 499 500 #if defined(CONFIG_CMD_KGDB) 501 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 502 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 503 #endif 504 505 /* 506 * Environment Configuration 507 */ 508 509 /* The mac addresses for all ethernet interface */ 510 #if defined(CONFIG_TSEC_ENET) 511 #define CONFIG_HAS_ETH0 512 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 513 #define CONFIG_HAS_ETH1 514 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 515 #define CONFIG_HAS_ETH2 516 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 517 #define CONFIG_HAS_ETH3 518 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 519 #endif 520 521 #define CONFIG_IPADDR 192.168.1.253 522 523 #define CONFIG_HOSTNAME unknown 524 #define CONFIG_ROOTPATH /nfsroot 525 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 526 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 527 528 #define CONFIG_SERVERIP 192.168.1.1 529 #define CONFIG_GATEWAYIP 192.168.1.1 530 #define CONFIG_NETMASK 255.255.255.0 531 532 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 533 534 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 535 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 536 537 #define CONFIG_BAUDRATE 115200 538 539 #define CONFIG_EXTRA_ENV_SETTINGS \ 540 "netdev=eth0\0" \ 541 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 542 "tftpflash=tftpboot $loadaddr $uboot; " \ 543 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 544 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 545 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 546 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 547 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 548 "consoledev=ttyS1\0" \ 549 "ramdiskaddr=2000000\0" \ 550 "ramdiskfile=ramdisk.uboot\0" \ 551 "fdtaddr=c00000\0" \ 552 "fdtfile=mpc8548cds.dtb\0" 553 554 #define CONFIG_NFSBOOTCOMMAND \ 555 "setenv bootargs root=/dev/nfs rw " \ 556 "nfsroot=$serverip:$rootpath " \ 557 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 558 "console=$consoledev,$baudrate $othbootargs;" \ 559 "tftp $loadaddr $bootfile;" \ 560 "tftp $fdtaddr $fdtfile;" \ 561 "bootm $loadaddr - $fdtaddr" 562 563 564 #define CONFIG_RAMBOOTCOMMAND \ 565 "setenv bootargs root=/dev/ram rw " \ 566 "console=$consoledev,$baudrate $othbootargs;" \ 567 "tftp $ramdiskaddr $ramdiskfile;" \ 568 "tftp $loadaddr $bootfile;" \ 569 "tftp $fdtaddr $fdtfile;" \ 570 "bootm $loadaddr $ramdiskaddr $fdtaddr" 571 572 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 573 574 #endif /* __CONFIG_H */ 575