1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xfff80000 41 #endif 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 46 #define CONFIG_PCI /* enable any pci type devices */ 47 #define CONFIG_PCI1 /* PCI controller 1 */ 48 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 49 #undef CONFIG_PCI2 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 58 59 #define CONFIG_FSL_VIA 60 61 #ifndef __ASSEMBLY__ 62 extern unsigned long get_clock_freq(void); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 #define CONFIG_SYS_CCSRBAR 0xe0000000 81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 82 83 /* DDR Setup */ 84 #define CONFIG_FSL_DDR2 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 87 #define CONFIG_DDR_SPD 88 89 #define CONFIG_DDR_ECC 90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 92 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_NUM_DDR_CONTROLLERS 1 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 98 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 99 100 /* I2C addresses of SPD EEPROMs */ 101 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 102 103 /* Make sure required options are set */ 104 #ifndef CONFIG_SPD_EEPROM 105 #error ("CONFIG_SPD_EEPROM is required") 106 #endif 107 108 #undef CONFIG_CLOCKS_IN_MHZ 109 110 /* 111 * Local Bus Definitions 112 */ 113 114 /* 115 * FLASH on the Local Bus 116 * Two banks, 8M each, using the CFI driver. 117 * Boot from BR0/OR0 bank at 0xff00_0000 118 * Alternate BR1/OR1 bank at 0xff80_0000 119 * 120 * BR0, BR1: 121 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 122 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 123 * Port Size = 16 bits = BRx[19:20] = 10 124 * Use GPCM = BRx[24:26] = 000 125 * Valid = BRx[31] = 1 126 * 127 * 0 4 8 12 16 20 24 28 128 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 129 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 130 * 131 * OR0, OR1: 132 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 133 * Reserved ORx[17:18] = 11, confusion here? 134 * CSNT = ORx[20] = 1 135 * ACS = half cycle delay = ORx[21:22] = 11 136 * SCY = 6 = ORx[24:27] = 0110 137 * TRLX = use relaxed timing = ORx[29] = 1 138 * EAD = use external address latch delay = OR[31] = 1 139 * 140 * 0 4 8 12 16 20 24 28 141 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 142 */ 143 144 #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ 145 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 146 147 #define CONFIG_SYS_BR0_PRELIM 0xff801001 148 #define CONFIG_SYS_BR1_PRELIM 0xff001001 149 150 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 151 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 152 153 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 154 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 155 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 156 #undef CONFIG_SYS_FLASH_CHECKSUM 157 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 158 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 159 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 161 162 #define CONFIG_FLASH_CFI_DRIVER 163 #define CONFIG_SYS_FLASH_CFI 164 #define CONFIG_SYS_FLASH_EMPTY_INFO 165 166 #define CONFIG_HWCONFIG /* enable hwconfig */ 167 168 /* 169 * SDRAM on the Local Bus 170 */ 171 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 172 #define CONFIG_SYS_LBC_CACHE_SIZE 64 173 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 174 #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 175 176 #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ 177 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 178 179 /* 180 * Base Register 2 and Option Register 2 configure SDRAM. 181 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 182 * 183 * For BR2, need: 184 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 185 * port-size = 32-bits = BR2[19:20] = 11 186 * no parity checking = BR2[21:22] = 00 187 * SDRAM for MSEL = BR2[24:26] = 011 188 * Valid = BR[31] = 1 189 * 190 * 0 4 8 12 16 20 24 28 191 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 192 * 193 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 194 * FIXME: the top 17 bits of BR2. 195 */ 196 197 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 198 199 /* 200 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 201 * 202 * For OR2, need: 203 * 64MB mask for AM, OR2[0:7] = 1111 1100 204 * XAM, OR2[17:18] = 11 205 * 9 columns OR2[19-21] = 010 206 * 13 rows OR2[23-25] = 100 207 * EAD set for extra time OR[31] = 1 208 * 209 * 0 4 8 12 16 20 24 28 210 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 211 */ 212 213 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 214 215 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 216 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 217 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 218 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 219 220 /* 221 * Common settings for all Local Bus SDRAM commands. 222 * At run time, either BSMA1516 (for CPU 1.1) 223 * or BSMA1617 (for CPU 1.0) (old) 224 * is OR'ed in too. 225 */ 226 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 227 | LSDMR_PRETOACT7 \ 228 | LSDMR_ACTTORW7 \ 229 | LSDMR_BL8 \ 230 | LSDMR_WRC4 \ 231 | LSDMR_CL3 \ 232 | LSDMR_RFEN \ 233 ) 234 235 /* 236 * The CADMUS registers are connected to CS3 on CDS. 237 * The new memory map places CADMUS at 0xf8000000. 238 * 239 * For BR3, need: 240 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 241 * port-size = 8-bits = BR[19:20] = 01 242 * no parity checking = BR[21:22] = 00 243 * GPMC for MSEL = BR[24:26] = 000 244 * Valid = BR[31] = 1 245 * 246 * 0 4 8 12 16 20 24 28 247 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 248 * 249 * For OR3, need: 250 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 251 * disable buffer ctrl OR[19] = 0 252 * CSNT OR[20] = 1 253 * ACS OR[21:22] = 11 254 * XACS OR[23] = 1 255 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 256 * SETA OR[28] = 0 257 * TRLX OR[29] = 1 258 * EHTR OR[30] = 1 259 * EAD extra time OR[31] = 1 260 * 261 * 0 4 8 12 16 20 24 28 262 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 263 */ 264 265 #define CONFIG_FSL_CADMUS 266 267 #define CADMUS_BASE_ADDR 0xf8000000 268 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 269 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 270 271 #define CONFIG_SYS_INIT_RAM_LOCK 1 272 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 273 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 274 275 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 276 277 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 278 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 279 280 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 281 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 282 283 /* Serial Port */ 284 #define CONFIG_CONS_INDEX 2 285 #define CONFIG_SYS_NS16550 286 #define CONFIG_SYS_NS16550_SERIAL 287 #define CONFIG_SYS_NS16550_REG_SIZE 1 288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 289 290 #define CONFIG_SYS_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 292 293 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 294 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 295 296 /* Use the HUSH parser */ 297 #define CONFIG_SYS_HUSH_PARSER 298 #ifdef CONFIG_SYS_HUSH_PARSER 299 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 300 #endif 301 302 /* pass open firmware flat tree */ 303 #define CONFIG_OF_LIBFDT 1 304 #define CONFIG_OF_BOARD_SETUP 1 305 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 306 307 /* 308 * I2C 309 */ 310 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 311 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 312 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 313 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 314 #define CONFIG_SYS_I2C_SLAVE 0x7F 315 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 316 #define CONFIG_SYS_I2C_OFFSET 0x3000 317 318 /* EEPROM */ 319 #define CONFIG_ID_EEPROM 320 #define CONFIG_SYS_I2C_EEPROM_CCID 321 #define CONFIG_SYS_ID_EEPROM 322 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 324 325 /* 326 * General PCI 327 * Memory space is mapped 1-1, but I/O space must start from 0. 328 */ 329 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 330 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 331 332 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 333 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 334 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 335 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 336 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 337 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 338 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 339 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 340 341 #ifdef CONFIG_PCI2 342 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 343 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 344 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 345 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 346 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 347 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 348 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 349 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 350 #endif 351 352 #ifdef CONFIG_PCIE1 353 #define CONFIG_SYS_PCIE1_NAME "Slot" 354 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 355 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 356 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 357 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 358 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 359 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 360 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 361 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 362 #endif 363 364 /* 365 * RapidIO MMU 366 */ 367 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 368 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 369 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 370 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 371 372 #ifdef CONFIG_LEGACY 373 #define BRIDGE_ID 17 374 #define VIA_ID 2 375 #else 376 #define BRIDGE_ID 28 377 #define VIA_ID 4 378 #endif 379 380 #if defined(CONFIG_PCI) 381 382 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 383 384 #undef CONFIG_EEPRO100 385 #undef CONFIG_TULIP 386 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 387 388 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 389 390 #endif /* CONFIG_PCI */ 391 392 393 #if defined(CONFIG_TSEC_ENET) 394 395 #define CONFIG_MII 1 /* MII PHY management */ 396 #define CONFIG_TSEC1 1 397 #define CONFIG_TSEC1_NAME "eTSEC0" 398 #define CONFIG_TSEC2 1 399 #define CONFIG_TSEC2_NAME "eTSEC1" 400 #define CONFIG_TSEC3 1 401 #define CONFIG_TSEC3_NAME "eTSEC2" 402 #define CONFIG_TSEC4 403 #define CONFIG_TSEC4_NAME "eTSEC3" 404 #undef CONFIG_MPC85XX_FEC 405 406 #define TSEC1_PHY_ADDR 0 407 #define TSEC2_PHY_ADDR 1 408 #define TSEC3_PHY_ADDR 2 409 #define TSEC4_PHY_ADDR 3 410 411 #define TSEC1_PHYIDX 0 412 #define TSEC2_PHYIDX 0 413 #define TSEC3_PHYIDX 0 414 #define TSEC4_PHYIDX 0 415 #define TSEC1_FLAGS TSEC_GIGABIT 416 #define TSEC2_FLAGS TSEC_GIGABIT 417 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 420 /* Options are: eTSEC[0-3] */ 421 #define CONFIG_ETHPRIME "eTSEC0" 422 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 423 #endif /* CONFIG_TSEC_ENET */ 424 425 /* 426 * Environment 427 */ 428 #define CONFIG_ENV_IS_IN_FLASH 1 429 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 430 #define CONFIG_ENV_ADDR 0xfff80000 431 #else 432 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 433 #endif 434 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 435 #define CONFIG_ENV_SIZE 0x2000 436 437 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 438 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 439 440 /* 441 * BOOTP options 442 */ 443 #define CONFIG_BOOTP_BOOTFILESIZE 444 #define CONFIG_BOOTP_BOOTPATH 445 #define CONFIG_BOOTP_GATEWAY 446 #define CONFIG_BOOTP_HOSTNAME 447 448 449 /* 450 * Command line configuration. 451 */ 452 #include <config_cmd_default.h> 453 454 #define CONFIG_CMD_PING 455 #define CONFIG_CMD_I2C 456 #define CONFIG_CMD_MII 457 #define CONFIG_CMD_ELF 458 #define CONFIG_CMD_IRQ 459 #define CONFIG_CMD_SETEXPR 460 #define CONFIG_CMD_REGINFO 461 462 #if defined(CONFIG_PCI) 463 #define CONFIG_CMD_PCI 464 #endif 465 466 467 #undef CONFIG_WATCHDOG /* watchdog disabled */ 468 469 /* 470 * Miscellaneous configurable options 471 */ 472 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 473 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 474 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 475 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 476 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 477 #if defined(CONFIG_CMD_KGDB) 478 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 479 #else 480 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 481 #endif 482 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 483 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 484 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 485 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 486 487 /* 488 * For booting Linux, the board info and command line data 489 * have to be in the first 64 MB of memory, since this is 490 * the maximum mapped by the Linux kernel during initialization. 491 */ 492 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 493 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 494 495 #if defined(CONFIG_CMD_KGDB) 496 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 497 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 498 #endif 499 500 /* 501 * Environment Configuration 502 */ 503 504 /* The mac addresses for all ethernet interface */ 505 #if defined(CONFIG_TSEC_ENET) 506 #define CONFIG_HAS_ETH0 507 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 508 #define CONFIG_HAS_ETH1 509 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 510 #define CONFIG_HAS_ETH2 511 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 512 #define CONFIG_HAS_ETH3 513 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 514 #endif 515 516 #define CONFIG_IPADDR 192.168.1.253 517 518 #define CONFIG_HOSTNAME unknown 519 #define CONFIG_ROOTPATH /nfsroot 520 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 521 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 522 523 #define CONFIG_SERVERIP 192.168.1.1 524 #define CONFIG_GATEWAYIP 192.168.1.1 525 #define CONFIG_NETMASK 255.255.255.0 526 527 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 528 529 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 530 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 531 532 #define CONFIG_BAUDRATE 115200 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "hwconfig=fsl_ddr:ecc=off\0" \ 536 "netdev=eth0\0" \ 537 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 538 "tftpflash=tftpboot $loadaddr $uboot; " \ 539 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 540 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 541 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 542 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 543 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 544 "consoledev=ttyS1\0" \ 545 "ramdiskaddr=2000000\0" \ 546 "ramdiskfile=ramdisk.uboot\0" \ 547 "fdtaddr=c00000\0" \ 548 "fdtfile=mpc8548cds.dtb\0" 549 550 #define CONFIG_NFSBOOTCOMMAND \ 551 "setenv bootargs root=/dev/nfs rw " \ 552 "nfsroot=$serverip:$rootpath " \ 553 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 554 "console=$consoledev,$baudrate $othbootargs;" \ 555 "tftp $loadaddr $bootfile;" \ 556 "tftp $fdtaddr $fdtfile;" \ 557 "bootm $loadaddr - $fdtaddr" 558 559 560 #define CONFIG_RAMBOOTCOMMAND \ 561 "setenv bootargs root=/dev/ram rw " \ 562 "console=$consoledev,$baudrate $othbootargs;" \ 563 "tftp $ramdiskaddr $ramdiskfile;" \ 564 "tftp $loadaddr $bootfile;" \ 565 "tftp $fdtaddr $fdtfile;" \ 566 "bootm $loadaddr $ramdiskaddr $fdtaddr" 567 568 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 569 570 #endif /* __CONFIG_H */ 571