1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #ifndef CONFIG_SYS_TEXT_BASE 17 #define CONFIG_SYS_TEXT_BASE 0xfff80000 18 #endif 19 20 #define CONFIG_SYS_SRIO 21 #define CONFIG_SRIO1 /* SRIO port 1 */ 22 23 #define CONFIG_PCI1 /* PCI controller 1 */ 24 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 25 #undef CONFIG_PCI2 26 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 28 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 31 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 32 #define CONFIG_ENV_OVERWRITE 33 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 34 35 #define CONFIG_FSL_VIA 36 37 #ifndef __ASSEMBLY__ 38 extern unsigned long get_clock_freq(void); 39 #endif 40 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 41 42 /* 43 * These can be toggled for performance analysis, otherwise use default. 44 */ 45 #define CONFIG_L2_CACHE /* toggle L2 cache */ 46 #define CONFIG_BTB /* toggle branch predition */ 47 48 /* 49 * Only possible on E500 Version 2 or newer cores. 50 */ 51 #define CONFIG_ENABLE_36BIT_PHYS 1 52 53 #ifdef CONFIG_PHYS_64BIT 54 #define CONFIG_ADDR_MAP 55 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 56 #endif 57 58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 59 #define CONFIG_SYS_MEMTEST_END 0x00400000 60 61 #define CONFIG_SYS_CCSRBAR 0xe0000000 62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 63 64 /* DDR Setup */ 65 #undef CONFIG_FSL_DDR_INTERACTIVE 66 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 67 #define CONFIG_DDR_SPD 68 69 #define CONFIG_DDR_ECC 70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 72 73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 75 76 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 77 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 78 79 /* I2C addresses of SPD EEPROMs */ 80 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 81 82 /* Make sure required options are set */ 83 #ifndef CONFIG_SPD_EEPROM 84 #error ("CONFIG_SPD_EEPROM is required") 85 #endif 86 87 #undef CONFIG_CLOCKS_IN_MHZ 88 /* 89 * Physical Address Map 90 * 91 * 32bit: 92 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 93 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 94 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 95 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 96 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 97 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 98 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 99 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 100 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 101 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 102 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 103 * 104 * 36bit: 105 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 106 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 107 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 108 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 109 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 110 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 111 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 112 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 113 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 114 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 115 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 116 * 117 */ 118 119 /* 120 * Local Bus Definitions 121 */ 122 123 /* 124 * FLASH on the Local Bus 125 * Two banks, 8M each, using the CFI driver. 126 * Boot from BR0/OR0 bank at 0xff00_0000 127 * Alternate BR1/OR1 bank at 0xff80_0000 128 * 129 * BR0, BR1: 130 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 131 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 132 * Port Size = 16 bits = BRx[19:20] = 10 133 * Use GPCM = BRx[24:26] = 000 134 * Valid = BRx[31] = 1 135 * 136 * 0 4 8 12 16 20 24 28 137 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 138 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 139 * 140 * OR0, OR1: 141 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 142 * Reserved ORx[17:18] = 11, confusion here? 143 * CSNT = ORx[20] = 1 144 * ACS = half cycle delay = ORx[21:22] = 11 145 * SCY = 6 = ORx[24:27] = 0110 146 * TRLX = use relaxed timing = ORx[29] = 1 147 * EAD = use external address latch delay = OR[31] = 1 148 * 149 * 0 4 8 12 16 20 24 28 150 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 151 */ 152 153 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 156 #else 157 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 158 #endif 159 160 #define CONFIG_SYS_BR0_PRELIM \ 161 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 162 #define CONFIG_SYS_BR1_PRELIM \ 163 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 164 165 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 166 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 167 168 #define CONFIG_SYS_FLASH_BANKS_LIST \ 169 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 170 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 171 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 172 #undef CONFIG_SYS_FLASH_CHECKSUM 173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 175 176 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 177 178 #define CONFIG_FLASH_CFI_DRIVER 179 #define CONFIG_SYS_FLASH_CFI 180 #define CONFIG_SYS_FLASH_EMPTY_INFO 181 182 #define CONFIG_HWCONFIG /* enable hwconfig */ 183 184 /* 185 * SDRAM on the Local Bus 186 */ 187 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 188 #ifdef CONFIG_PHYS_64BIT 189 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 190 #else 191 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 192 #endif 193 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 194 195 /* 196 * Base Register 2 and Option Register 2 configure SDRAM. 197 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 198 * 199 * For BR2, need: 200 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 201 * port-size = 32-bits = BR2[19:20] = 11 202 * no parity checking = BR2[21:22] = 00 203 * SDRAM for MSEL = BR2[24:26] = 011 204 * Valid = BR[31] = 1 205 * 206 * 0 4 8 12 16 20 24 28 207 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 208 * 209 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 210 * FIXME: the top 17 bits of BR2. 211 */ 212 213 #define CONFIG_SYS_BR2_PRELIM \ 214 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 215 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 216 217 /* 218 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 219 * 220 * For OR2, need: 221 * 64MB mask for AM, OR2[0:7] = 1111 1100 222 * XAM, OR2[17:18] = 11 223 * 9 columns OR2[19-21] = 010 224 * 13 rows OR2[23-25] = 100 225 * EAD set for extra time OR[31] = 1 226 * 227 * 0 4 8 12 16 20 24 28 228 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 229 */ 230 231 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 232 233 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 234 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 235 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 236 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 237 238 /* 239 * Common settings for all Local Bus SDRAM commands. 240 * At run time, either BSMA1516 (for CPU 1.1) 241 * or BSMA1617 (for CPU 1.0) (old) 242 * is OR'ed in too. 243 */ 244 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 245 | LSDMR_PRETOACT7 \ 246 | LSDMR_ACTTORW7 \ 247 | LSDMR_BL8 \ 248 | LSDMR_WRC4 \ 249 | LSDMR_CL3 \ 250 | LSDMR_RFEN \ 251 ) 252 253 /* 254 * The CADMUS registers are connected to CS3 on CDS. 255 * The new memory map places CADMUS at 0xf8000000. 256 * 257 * For BR3, need: 258 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 259 * port-size = 8-bits = BR[19:20] = 01 260 * no parity checking = BR[21:22] = 00 261 * GPMC for MSEL = BR[24:26] = 000 262 * Valid = BR[31] = 1 263 * 264 * 0 4 8 12 16 20 24 28 265 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 266 * 267 * For OR3, need: 268 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 269 * disable buffer ctrl OR[19] = 0 270 * CSNT OR[20] = 1 271 * ACS OR[21:22] = 11 272 * XACS OR[23] = 1 273 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 274 * SETA OR[28] = 0 275 * TRLX OR[29] = 1 276 * EHTR OR[30] = 1 277 * EAD extra time OR[31] = 1 278 * 279 * 0 4 8 12 16 20 24 28 280 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 281 */ 282 283 #define CONFIG_FSL_CADMUS 284 285 #define CADMUS_BASE_ADDR 0xf8000000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 288 #else 289 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 290 #endif 291 #define CONFIG_SYS_BR3_PRELIM \ 292 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 293 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 294 295 #define CONFIG_SYS_INIT_RAM_LOCK 1 296 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 297 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 298 299 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 300 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 301 302 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 303 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 304 305 /* Serial Port */ 306 #define CONFIG_CONS_INDEX 2 307 #define CONFIG_SYS_NS16550_SERIAL 308 #define CONFIG_SYS_NS16550_REG_SIZE 1 309 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 310 311 #define CONFIG_SYS_BAUDRATE_TABLE \ 312 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 313 314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 316 317 /* 318 * I2C 319 */ 320 #define CONFIG_SYS_I2C 321 #define CONFIG_SYS_I2C_FSL 322 #define CONFIG_SYS_FSL_I2C_SPEED 400000 323 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 324 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 325 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 326 327 /* EEPROM */ 328 #define CONFIG_ID_EEPROM 329 #define CONFIG_SYS_I2C_EEPROM_CCID 330 #define CONFIG_SYS_ID_EEPROM 331 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 332 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 333 334 /* 335 * General PCI 336 * Memory space is mapped 1-1, but I/O space must start from 0. 337 */ 338 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 339 #ifdef CONFIG_PHYS_64BIT 340 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 341 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 342 #else 343 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 344 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 345 #endif 346 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 347 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 348 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 349 #ifdef CONFIG_PHYS_64BIT 350 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 351 #else 352 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 353 #endif 354 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 355 356 #ifdef CONFIG_PCIE1 357 #define CONFIG_SYS_PCIE1_NAME "Slot" 358 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 361 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 362 #else 363 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 364 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 365 #endif 366 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 367 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 368 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 369 #ifdef CONFIG_PHYS_64BIT 370 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 371 #else 372 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 373 #endif 374 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 375 #endif 376 377 /* 378 * RapidIO MMU 379 */ 380 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 381 #ifdef CONFIG_PHYS_64BIT 382 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 383 #else 384 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 385 #endif 386 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 387 388 #ifdef CONFIG_LEGACY 389 #define BRIDGE_ID 17 390 #define VIA_ID 2 391 #else 392 #define BRIDGE_ID 28 393 #define VIA_ID 4 394 #endif 395 396 #if defined(CONFIG_PCI) 397 #undef CONFIG_EEPRO100 398 #undef CONFIG_TULIP 399 400 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 401 402 #endif /* CONFIG_PCI */ 403 404 #if defined(CONFIG_TSEC_ENET) 405 406 #define CONFIG_MII 1 /* MII PHY management */ 407 #define CONFIG_TSEC1 1 408 #define CONFIG_TSEC1_NAME "eTSEC0" 409 #define CONFIG_TSEC2 1 410 #define CONFIG_TSEC2_NAME "eTSEC1" 411 #define CONFIG_TSEC3 1 412 #define CONFIG_TSEC3_NAME "eTSEC2" 413 #define CONFIG_TSEC4 414 #define CONFIG_TSEC4_NAME "eTSEC3" 415 #undef CONFIG_MPC85XX_FEC 416 417 #define CONFIG_PHY_MARVELL 418 419 #define TSEC1_PHY_ADDR 0 420 #define TSEC2_PHY_ADDR 1 421 #define TSEC3_PHY_ADDR 2 422 #define TSEC4_PHY_ADDR 3 423 424 #define TSEC1_PHYIDX 0 425 #define TSEC2_PHYIDX 0 426 #define TSEC3_PHYIDX 0 427 #define TSEC4_PHYIDX 0 428 #define TSEC1_FLAGS TSEC_GIGABIT 429 #define TSEC2_FLAGS TSEC_GIGABIT 430 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 431 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 432 433 /* Options are: eTSEC[0-3] */ 434 #define CONFIG_ETHPRIME "eTSEC0" 435 #endif /* CONFIG_TSEC_ENET */ 436 437 /* 438 * Environment 439 */ 440 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 441 #define CONFIG_ENV_ADDR 0xfff80000 442 #else 443 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 444 #endif 445 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 446 #define CONFIG_ENV_SIZE 0x2000 447 448 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 449 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 450 451 /* 452 * BOOTP options 453 */ 454 #define CONFIG_BOOTP_BOOTFILESIZE 455 #define CONFIG_BOOTP_BOOTPATH 456 #define CONFIG_BOOTP_GATEWAY 457 #define CONFIG_BOOTP_HOSTNAME 458 459 #undef CONFIG_WATCHDOG /* watchdog disabled */ 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 465 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 466 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 467 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 468 #if defined(CONFIG_CMD_KGDB) 469 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 470 #else 471 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 472 #endif 473 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 474 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 475 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 476 477 /* 478 * For booting Linux, the board info and command line data 479 * have to be in the first 64 MB of memory, since this is 480 * the maximum mapped by the Linux kernel during initialization. 481 */ 482 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 483 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 484 485 #if defined(CONFIG_CMD_KGDB) 486 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 487 #endif 488 489 /* 490 * Environment Configuration 491 */ 492 #if defined(CONFIG_TSEC_ENET) 493 #define CONFIG_HAS_ETH0 494 #define CONFIG_HAS_ETH1 495 #define CONFIG_HAS_ETH2 496 #define CONFIG_HAS_ETH3 497 #endif 498 499 #define CONFIG_IPADDR 192.168.1.253 500 501 #define CONFIG_HOSTNAME unknown 502 #define CONFIG_ROOTPATH "/nfsroot" 503 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 504 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 505 506 #define CONFIG_SERVERIP 192.168.1.1 507 #define CONFIG_GATEWAYIP 192.168.1.1 508 #define CONFIG_NETMASK 255.255.255.0 509 510 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 511 512 #define CONFIG_EXTRA_ENV_SETTINGS \ 513 "hwconfig=fsl_ddr:ecc=off\0" \ 514 "netdev=eth0\0" \ 515 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 516 "tftpflash=tftpboot $loadaddr $uboot; " \ 517 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 518 " +$filesize; " \ 519 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 520 " +$filesize; " \ 521 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 522 " $filesize; " \ 523 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 524 " +$filesize; " \ 525 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 526 " $filesize\0" \ 527 "consoledev=ttyS1\0" \ 528 "ramdiskaddr=2000000\0" \ 529 "ramdiskfile=ramdisk.uboot\0" \ 530 "fdtaddr=1e00000\0" \ 531 "fdtfile=mpc8548cds.dtb\0" 532 533 #define CONFIG_NFSBOOTCOMMAND \ 534 "setenv bootargs root=/dev/nfs rw " \ 535 "nfsroot=$serverip:$rootpath " \ 536 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 537 "console=$consoledev,$baudrate $othbootargs;" \ 538 "tftp $loadaddr $bootfile;" \ 539 "tftp $fdtaddr $fdtfile;" \ 540 "bootm $loadaddr - $fdtaddr" 541 542 #define CONFIG_RAMBOOTCOMMAND \ 543 "setenv bootargs root=/dev/ram rw " \ 544 "console=$consoledev,$baudrate $othbootargs;" \ 545 "tftp $ramdiskaddr $ramdiskfile;" \ 546 "tftp $loadaddr $bootfile;" \ 547 "tftp $fdtaddr $fdtfile;" \ 548 "bootm $loadaddr $ramdiskaddr $fdtaddr" 549 550 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 551 552 #endif /* __CONFIG_H */ 553