1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #define CONFIG_PCI /* enable any pci type devices */ 40 #define CONFIG_PCI1 /* PCI controller 1 */ 41 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 42 #undef CONFIG_RIO 43 #undef CONFIG_PCI2 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 46 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_ENV_OVERWRITE 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 50 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 51 #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 53 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 55 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 58 59 /* 60 * When initializing flash, if we cannot find the manufacturer ID, 61 * assume this is the AMD flash associated with the CDS board. 62 * This allows booting from a promjet. 63 */ 64 #define CONFIG_ASSUME_AMD_FLASH 65 66 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 67 68 #ifndef __ASSEMBLY__ 69 extern unsigned long get_clock_freq(void); 70 #endif 71 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 72 73 /* 74 * These can be toggled for performance analysis, otherwise use default. 75 */ 76 #define CONFIG_L2_CACHE /* toggle L2 cache */ 77 #define CONFIG_BTB /* toggle branch predition */ 78 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 79 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ 80 81 /* 82 * Only possible on E500 Version 2 or newer cores. 83 */ 84 #define CONFIG_ENABLE_36BIT_PHYS 1 85 86 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 87 88 #undef CFG_DRAM_TEST /* memory test, takes time */ 89 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ 90 #define CFG_MEMTEST_END 0x00400000 91 92 /* 93 * Base addresses -- Note these are effective addresses where the 94 * actual resources get mapped (not physical addresses) 95 */ 96 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 97 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 98 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 99 100 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 101 #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) 102 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 103 104 /* 105 * DDR Setup 106 */ 107 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 108 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 109 110 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 111 112 /* 113 * Make sure required options are set 114 */ 115 #ifndef CONFIG_SPD_EEPROM 116 #error ("CONFIG_SPD_EEPROM is required") 117 #endif 118 119 #undef CONFIG_CLOCKS_IN_MHZ 120 121 /* 122 * Local Bus Definitions 123 */ 124 125 /* 126 * FLASH on the Local Bus 127 * Two banks, 8M each, using the CFI driver. 128 * Boot from BR0/OR0 bank at 0xff00_0000 129 * Alternate BR1/OR1 bank at 0xff80_0000 130 * 131 * BR0, BR1: 132 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 133 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 134 * Port Size = 16 bits = BRx[19:20] = 10 135 * Use GPCM = BRx[24:26] = 000 136 * Valid = BRx[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 140 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 141 * 142 * OR0, OR1: 143 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 144 * Reserved ORx[17:18] = 11, confusion here? 145 * CSNT = ORx[20] = 1 146 * ACS = half cycle delay = ORx[21:22] = 11 147 * SCY = 6 = ORx[24:27] = 0110 148 * TRLX = use relaxed timing = ORx[29] = 1 149 * EAD = use external address latch delay = OR[31] = 1 150 * 151 * 0 4 8 12 16 20 24 28 152 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 153 */ 154 155 #define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ 156 #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ 157 158 #define CFG_BR0_PRELIM 0xff801001 159 #define CFG_BR1_PRELIM 0xff001001 160 161 #define CFG_OR0_PRELIM 0xff806e65 162 #define CFG_OR1_PRELIM 0xff806e65 163 164 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} 165 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 166 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 167 #undef CFG_FLASH_CHECKSUM 168 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 169 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 170 171 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 172 173 #define CFG_FLASH_CFI_DRIVER 174 #define CFG_FLASH_CFI 175 #define CFG_FLASH_EMPTY_INFO 176 177 178 /* 179 * SDRAM on the Local Bus 180 */ 181 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 182 #define CFG_LBC_CACHE_SIZE 64 183 #define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 184 #define CFG_LBC_NONCACHE_SIZE 64 185 186 #define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ 187 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 188 189 /* 190 * Base Register 2 and Option Register 2 configure SDRAM. 191 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. 192 * 193 * For BR2, need: 194 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 195 * port-size = 32-bits = BR2[19:20] = 11 196 * no parity checking = BR2[21:22] = 00 197 * SDRAM for MSEL = BR2[24:26] = 011 198 * Valid = BR[31] = 1 199 * 200 * 0 4 8 12 16 20 24 28 201 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 202 * 203 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into 204 * FIXME: the top 17 bits of BR2. 205 */ 206 207 #define CFG_BR2_PRELIM 0xf0001861 208 209 /* 210 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. 211 * 212 * For OR2, need: 213 * 64MB mask for AM, OR2[0:7] = 1111 1100 214 * XAM, OR2[17:18] = 11 215 * 9 columns OR2[19-21] = 010 216 * 13 rows OR2[23-25] = 100 217 * EAD set for extra time OR[31] = 1 218 * 219 * 0 4 8 12 16 20 24 28 220 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 221 */ 222 223 #define CFG_OR2_PRELIM 0xfc006901 224 225 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 226 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 227 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 228 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 229 230 /* 231 * LSDMR masks 232 */ 233 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) 234 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) 235 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) 236 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) 237 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) 238 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) 239 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) 240 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) 241 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) 242 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) 243 244 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) 245 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) 246 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) 247 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) 248 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) 249 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) 250 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) 251 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) 252 253 /* 254 * Common settings for all Local Bus SDRAM commands. 255 * At run time, either BSMA1516 (for CPU 1.1) 256 * or BSMA1617 (for CPU 1.0) (old) 257 * is OR'ed in too. 258 */ 259 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ 260 | CFG_LBC_LSDMR_PRETOACT7 \ 261 | CFG_LBC_LSDMR_ACTTORW7 \ 262 | CFG_LBC_LSDMR_BL8 \ 263 | CFG_LBC_LSDMR_WRC4 \ 264 | CFG_LBC_LSDMR_CL3 \ 265 | CFG_LBC_LSDMR_RFEN \ 266 ) 267 268 /* 269 * The CADMUS registers are connected to CS3 on CDS. 270 * The new memory map places CADMUS at 0xf8000000. 271 * 272 * For BR3, need: 273 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 274 * port-size = 8-bits = BR[19:20] = 01 275 * no parity checking = BR[21:22] = 00 276 * GPMC for MSEL = BR[24:26] = 000 277 * Valid = BR[31] = 1 278 * 279 * 0 4 8 12 16 20 24 28 280 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 281 * 282 * For OR3, need: 283 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 284 * disable buffer ctrl OR[19] = 0 285 * CSNT OR[20] = 1 286 * ACS OR[21:22] = 11 287 * XACS OR[23] = 1 288 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 289 * SETA OR[28] = 0 290 * TRLX OR[29] = 1 291 * EHTR OR[30] = 1 292 * EAD extra time OR[31] = 1 293 * 294 * 0 4 8 12 16 20 24 28 295 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 296 */ 297 298 #define CADMUS_BASE_ADDR 0xf8000000 299 #define CFG_BR3_PRELIM 0xf8000801 300 #define CFG_OR3_PRELIM 0xfff00ff7 301 302 #define CONFIG_L1_INIT_RAM 303 #define CFG_INIT_RAM_LOCK 1 304 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 305 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 306 307 #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 308 309 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 310 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 311 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 312 313 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 314 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 315 316 /* Serial Port */ 317 #define CONFIG_CONS_INDEX 2 318 #undef CONFIG_SERIAL_SOFTWARE_FIFO 319 #define CFG_NS16550 320 #define CFG_NS16550_SERIAL 321 #define CFG_NS16550_REG_SIZE 1 322 #define CFG_NS16550_CLK get_bus_freq(0) 323 324 #define CFG_BAUDRATE_TABLE \ 325 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 326 327 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 328 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 329 330 /* Use the HUSH parser */ 331 #define CFG_HUSH_PARSER 332 #ifdef CFG_HUSH_PARSER 333 #define CFG_PROMPT_HUSH_PS2 "> " 334 #endif 335 336 /* pass open firmware flat tree */ 337 #define CONFIG_OF_LIBFDT 1 338 #define CONFIG_OF_BOARD_SETUP 1 339 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 340 341 /* 342 * I2C 343 */ 344 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 345 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 346 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 347 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 348 #define CFG_I2C_EEPROM_ADDR 0x57 349 #define CFG_I2C_SLAVE 0x7F 350 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 351 #define CFG_I2C_OFFSET 0x3000 352 353 /* 354 * General PCI 355 * Memory space is mapped 1-1, but I/O space must start from 0. 356 */ 357 #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 358 359 #define CFG_PCI1_MEM_BASE 0x80000000 360 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 361 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 362 #define CFG_PCI1_IO_BASE 0x00000000 363 #define CFG_PCI1_IO_PHYS 0xe2000000 364 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 365 366 #ifdef CONFIG_PCI2 367 #define CFG_PCI2_MEM_BASE 0xa0000000 368 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 369 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 370 #define CFG_PCI2_IO_BASE 0x00000000 371 #define CFG_PCI2_IO_PHYS 0xe2800000 372 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 373 #endif 374 375 #ifdef CONFIG_PCIE1 376 #define CFG_PCIE1_MEM_BASE 0xa0000000 377 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 378 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 379 #define CFG_PCIE1_IO_BASE 0x00000000 380 #define CFG_PCIE1_IO_PHYS 0xe3000000 381 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 382 #endif 383 384 #ifdef CONFIG_RIO 385 /* 386 * RapidIO MMU 387 */ 388 #define CFG_RIO_MEM_BASE 0xC0000000 389 #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ 390 #endif 391 392 #ifdef CONFIG_LEGACY 393 #define BRIDGE_ID 17 394 #define VIA_ID 2 395 #else 396 #define BRIDGE_ID 28 397 #define VIA_ID 4 398 #endif 399 400 #if defined(CONFIG_PCI) 401 402 #define CONFIG_NET_MULTI 403 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 404 405 #undef CONFIG_EEPRO100 406 #undef CONFIG_TULIP 407 408 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 409 410 /* PCI view of System Memory */ 411 #define CFG_PCI_MEMORY_BUS 0x00000000 412 #define CFG_PCI_MEMORY_PHYS 0x00000000 413 #define CFG_PCI_MEMORY_SIZE 0x80000000 414 415 #endif /* CONFIG_PCI */ 416 417 418 #if defined(CONFIG_TSEC_ENET) 419 420 #ifndef CONFIG_NET_MULTI 421 #define CONFIG_NET_MULTI 1 422 #endif 423 424 #define CONFIG_MII 1 /* MII PHY management */ 425 #define CONFIG_TSEC1 1 426 #define CONFIG_TSEC1_NAME "eTSEC0" 427 #define CONFIG_TSEC2 1 428 #define CONFIG_TSEC2_NAME "eTSEC1" 429 #define CONFIG_TSEC3 1 430 #define CONFIG_TSEC3_NAME "eTSEC2" 431 #define CONFIG_TSEC4 432 #define CONFIG_TSEC4_NAME "eTSEC3" 433 #undef CONFIG_MPC85XX_FEC 434 435 #define TSEC1_PHY_ADDR 0 436 #define TSEC2_PHY_ADDR 1 437 #define TSEC3_PHY_ADDR 2 438 #define TSEC4_PHY_ADDR 3 439 440 #define TSEC1_PHYIDX 0 441 #define TSEC2_PHYIDX 0 442 #define TSEC3_PHYIDX 0 443 #define TSEC4_PHYIDX 0 444 #define TSEC1_FLAGS TSEC_GIGABIT 445 #define TSEC2_FLAGS TSEC_GIGABIT 446 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 447 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 448 449 /* Options are: eTSEC[0-3] */ 450 #define CONFIG_ETHPRIME "eTSEC0" 451 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 452 #endif /* CONFIG_TSEC_ENET */ 453 454 /* 455 * Environment 456 */ 457 #define CFG_ENV_IS_IN_FLASH 1 458 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 459 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 460 #define CFG_ENV_SIZE 0x2000 461 462 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 463 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 464 465 /* 466 * BOOTP options 467 */ 468 #define CONFIG_BOOTP_BOOTFILESIZE 469 #define CONFIG_BOOTP_BOOTPATH 470 #define CONFIG_BOOTP_GATEWAY 471 #define CONFIG_BOOTP_HOSTNAME 472 473 474 /* 475 * Command line configuration. 476 */ 477 #include <config_cmd_default.h> 478 479 #define CONFIG_CMD_PING 480 #define CONFIG_CMD_I2C 481 #define CONFIG_CMD_MII 482 #define CONFIG_CMD_ELF 483 484 #if defined(CONFIG_PCI) 485 #define CONFIG_CMD_PCI 486 #endif 487 488 489 #undef CONFIG_WATCHDOG /* watchdog disabled */ 490 491 /* 492 * Miscellaneous configurable options 493 */ 494 #define CFG_LONGHELP /* undef to save memory */ 495 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 496 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 497 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 498 #if defined(CONFIG_CMD_KGDB) 499 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 500 #else 501 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 502 #endif 503 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 504 #define CFG_MAXARGS 16 /* max number of command args */ 505 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 506 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 507 508 /* 509 * For booting Linux, the board info and command line data 510 * have to be in the first 8 MB of memory, since this is 511 * the maximum mapped by the Linux kernel during initialization. 512 */ 513 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 514 515 /* 516 * Internal Definitions 517 * 518 * Boot Flags 519 */ 520 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 521 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 522 523 #if defined(CONFIG_CMD_KGDB) 524 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 525 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 526 #endif 527 528 /* 529 * Environment Configuration 530 */ 531 532 /* The mac addresses for all ethernet interface */ 533 #if defined(CONFIG_TSEC_ENET) 534 #define CONFIG_HAS_ETH0 535 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 536 #define CONFIG_HAS_ETH1 537 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 538 #define CONFIG_HAS_ETH2 539 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 540 #define CONFIG_HAS_ETH3 541 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 542 #endif 543 544 #define CONFIG_IPADDR 192.168.1.253 545 546 #define CONFIG_HOSTNAME unknown 547 #define CONFIG_ROOTPATH /nfsroot 548 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 549 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 550 551 #define CONFIG_SERVERIP 192.168.1.1 552 #define CONFIG_GATEWAYIP 192.168.1.1 553 #define CONFIG_NETMASK 255.255.255.0 554 555 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 556 557 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 558 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 559 560 #define CONFIG_BAUDRATE 115200 561 562 #define CONFIG_EXTRA_ENV_SETTINGS \ 563 "netdev=eth0\0" \ 564 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 565 "tftpflash=tftpboot $loadaddr $uboot; " \ 566 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 567 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 568 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 569 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 570 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 571 "consoledev=ttyS1\0" \ 572 "ramdiskaddr=2000000\0" \ 573 "ramdiskfile=ramdisk.uboot\0" \ 574 "fdtaddr=c00000\0" \ 575 "fdtfile=mpc8548cds.dtb\0" 576 577 #define CONFIG_NFSBOOTCOMMAND \ 578 "setenv bootargs root=/dev/nfs rw " \ 579 "nfsroot=$serverip:$rootpath " \ 580 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 581 "console=$consoledev,$baudrate $othbootargs;" \ 582 "tftp $loadaddr $bootfile;" \ 583 "tftp $fdtaddr $fdtfile;" \ 584 "bootm $loadaddr - $fdtaddr" 585 586 587 #define CONFIG_RAMBOOTCOMMAND \ 588 "setenv bootargs root=/dev/ram rw " \ 589 "console=$consoledev,$baudrate $othbootargs;" \ 590 "tftp $ramdiskaddr $ramdiskfile;" \ 591 "tftp $loadaddr $bootfile;" \ 592 "tftp $fdtaddr $fdtfile;" \ 593 "bootm $loadaddr $ramdiskaddr $fdtaddr" 594 595 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 596 597 #endif /* __CONFIG_H */ 598