1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #ifdef CONFIG_36BIT 19 #define CONFIG_PHYS_64BIT 20 #endif 21 22 /* High Level Configuration Options */ 23 #define CONFIG_BOOKE 1 /* BOOKE */ 24 #define CONFIG_E500 1 /* BOOKE e500 family */ 25 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 26 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xfff80000 30 #endif 31 32 #define CONFIG_SYS_SRIO 33 #define CONFIG_SRIO1 /* SRIO port 1 */ 34 35 #define CONFIG_PCI /* enable any pci type devices */ 36 #define CONFIG_PCI1 /* PCI controller 1 */ 37 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 38 #undef CONFIG_PCI2 39 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 40 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 41 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 42 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 43 44 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 45 #define CONFIG_ENV_OVERWRITE 46 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 48 49 #define CONFIG_FSL_VIA 50 51 #ifndef __ASSEMBLY__ 52 extern unsigned long get_clock_freq(void); 53 #endif 54 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 55 56 /* 57 * These can be toggled for performance analysis, otherwise use default. 58 */ 59 #define CONFIG_L2_CACHE /* toggle L2 cache */ 60 #define CONFIG_BTB /* toggle branch predition */ 61 62 /* 63 * Only possible on E500 Version 2 or newer cores. 64 */ 65 #define CONFIG_ENABLE_36BIT_PHYS 1 66 67 #ifdef CONFIG_PHYS_64BIT 68 #define CONFIG_ADDR_MAP 69 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 70 #endif 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 73 #define CONFIG_SYS_MEMTEST_END 0x00400000 74 75 #define CONFIG_SYS_CCSRBAR 0xe0000000 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77 78 /* DDR Setup */ 79 #define CONFIG_SYS_FSL_DDR2 80 #undef CONFIG_FSL_DDR_INTERACTIVE 81 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 82 #define CONFIG_DDR_SPD 83 84 #define CONFIG_DDR_ECC 85 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 86 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 87 88 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 90 91 #define CONFIG_NUM_DDR_CONTROLLERS 1 92 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 93 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 94 95 /* I2C addresses of SPD EEPROMs */ 96 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 97 98 /* Make sure required options are set */ 99 #ifndef CONFIG_SPD_EEPROM 100 #error ("CONFIG_SPD_EEPROM is required") 101 #endif 102 103 #undef CONFIG_CLOCKS_IN_MHZ 104 /* 105 * Physical Address Map 106 * 107 * 32bit: 108 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 109 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 110 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 111 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 112 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 113 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 114 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 115 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 116 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 117 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 118 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 119 * 120 * 36bit: 121 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 122 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 123 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 124 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 125 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 126 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 127 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 128 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 129 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 130 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 131 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 132 * 133 */ 134 135 136 /* 137 * Local Bus Definitions 138 */ 139 140 /* 141 * FLASH on the Local Bus 142 * Two banks, 8M each, using the CFI driver. 143 * Boot from BR0/OR0 bank at 0xff00_0000 144 * Alternate BR1/OR1 bank at 0xff80_0000 145 * 146 * BR0, BR1: 147 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 148 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 149 * Port Size = 16 bits = BRx[19:20] = 10 150 * Use GPCM = BRx[24:26] = 000 151 * Valid = BRx[31] = 1 152 * 153 * 0 4 8 12 16 20 24 28 154 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 155 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 156 * 157 * OR0, OR1: 158 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 159 * Reserved ORx[17:18] = 11, confusion here? 160 * CSNT = ORx[20] = 1 161 * ACS = half cycle delay = ORx[21:22] = 11 162 * SCY = 6 = ORx[24:27] = 0110 163 * TRLX = use relaxed timing = ORx[29] = 1 164 * EAD = use external address latch delay = OR[31] = 1 165 * 166 * 0 4 8 12 16 20 24 28 167 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 168 */ 169 170 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 173 #else 174 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 175 #endif 176 177 #define CONFIG_SYS_BR0_PRELIM \ 178 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 179 #define CONFIG_SYS_BR1_PRELIM \ 180 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 181 182 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 183 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 184 185 #define CONFIG_SYS_FLASH_BANKS_LIST \ 186 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 187 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 188 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 189 #undef CONFIG_SYS_FLASH_CHECKSUM 190 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 192 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 194 195 #define CONFIG_FLASH_CFI_DRIVER 196 #define CONFIG_SYS_FLASH_CFI 197 #define CONFIG_SYS_FLASH_EMPTY_INFO 198 199 #define CONFIG_HWCONFIG /* enable hwconfig */ 200 201 /* 202 * SDRAM on the Local Bus 203 */ 204 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 205 #ifdef CONFIG_PHYS_64BIT 206 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 207 #else 208 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 209 #endif 210 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 211 212 /* 213 * Base Register 2 and Option Register 2 configure SDRAM. 214 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 215 * 216 * For BR2, need: 217 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 218 * port-size = 32-bits = BR2[19:20] = 11 219 * no parity checking = BR2[21:22] = 00 220 * SDRAM for MSEL = BR2[24:26] = 011 221 * Valid = BR[31] = 1 222 * 223 * 0 4 8 12 16 20 24 28 224 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 225 * 226 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 227 * FIXME: the top 17 bits of BR2. 228 */ 229 230 #define CONFIG_SYS_BR2_PRELIM \ 231 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 232 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 233 234 /* 235 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 236 * 237 * For OR2, need: 238 * 64MB mask for AM, OR2[0:7] = 1111 1100 239 * XAM, OR2[17:18] = 11 240 * 9 columns OR2[19-21] = 010 241 * 13 rows OR2[23-25] = 100 242 * EAD set for extra time OR[31] = 1 243 * 244 * 0 4 8 12 16 20 24 28 245 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 246 */ 247 248 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 249 250 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 251 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 252 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 253 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 254 255 /* 256 * Common settings for all Local Bus SDRAM commands. 257 * At run time, either BSMA1516 (for CPU 1.1) 258 * or BSMA1617 (for CPU 1.0) (old) 259 * is OR'ed in too. 260 */ 261 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 262 | LSDMR_PRETOACT7 \ 263 | LSDMR_ACTTORW7 \ 264 | LSDMR_BL8 \ 265 | LSDMR_WRC4 \ 266 | LSDMR_CL3 \ 267 | LSDMR_RFEN \ 268 ) 269 270 /* 271 * The CADMUS registers are connected to CS3 on CDS. 272 * The new memory map places CADMUS at 0xf8000000. 273 * 274 * For BR3, need: 275 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 276 * port-size = 8-bits = BR[19:20] = 01 277 * no parity checking = BR[21:22] = 00 278 * GPMC for MSEL = BR[24:26] = 000 279 * Valid = BR[31] = 1 280 * 281 * 0 4 8 12 16 20 24 28 282 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 283 * 284 * For OR3, need: 285 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 286 * disable buffer ctrl OR[19] = 0 287 * CSNT OR[20] = 1 288 * ACS OR[21:22] = 11 289 * XACS OR[23] = 1 290 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 291 * SETA OR[28] = 0 292 * TRLX OR[29] = 1 293 * EHTR OR[30] = 1 294 * EAD extra time OR[31] = 1 295 * 296 * 0 4 8 12 16 20 24 28 297 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 298 */ 299 300 #define CONFIG_FSL_CADMUS 301 302 #define CADMUS_BASE_ADDR 0xf8000000 303 #ifdef CONFIG_PHYS_64BIT 304 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 305 #else 306 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 307 #endif 308 #define CONFIG_SYS_BR3_PRELIM \ 309 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 310 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 311 312 #define CONFIG_SYS_INIT_RAM_LOCK 1 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 314 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 315 316 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 317 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 318 319 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 320 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 321 322 /* Serial Port */ 323 #define CONFIG_CONS_INDEX 2 324 #define CONFIG_SYS_NS16550_SERIAL 325 #define CONFIG_SYS_NS16550_REG_SIZE 1 326 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 327 328 #define CONFIG_SYS_BAUDRATE_TABLE \ 329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 330 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 333 334 /* Use the HUSH parser */ 335 #define CONFIG_SYS_HUSH_PARSER 336 337 /* 338 * I2C 339 */ 340 #define CONFIG_SYS_I2C 341 #define CONFIG_SYS_I2C_FSL 342 #define CONFIG_SYS_FSL_I2C_SPEED 400000 343 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 344 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 345 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 346 347 /* EEPROM */ 348 #define CONFIG_ID_EEPROM 349 #define CONFIG_SYS_I2C_EEPROM_CCID 350 #define CONFIG_SYS_ID_EEPROM 351 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 352 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 353 354 /* 355 * General PCI 356 * Memory space is mapped 1-1, but I/O space must start from 0. 357 */ 358 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 361 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 362 #else 363 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 364 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 365 #endif 366 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 367 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 368 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 369 #ifdef CONFIG_PHYS_64BIT 370 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 371 #else 372 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 373 #endif 374 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 375 376 #ifdef CONFIG_PCIE1 377 #define CONFIG_SYS_PCIE1_NAME "Slot" 378 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 379 #ifdef CONFIG_PHYS_64BIT 380 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 381 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 382 #else 383 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 384 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 385 #endif 386 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 387 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 388 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 389 #ifdef CONFIG_PHYS_64BIT 390 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 391 #else 392 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 393 #endif 394 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 395 #endif 396 397 /* 398 * RapidIO MMU 399 */ 400 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 401 #ifdef CONFIG_PHYS_64BIT 402 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 403 #else 404 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 405 #endif 406 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 407 408 #ifdef CONFIG_LEGACY 409 #define BRIDGE_ID 17 410 #define VIA_ID 2 411 #else 412 #define BRIDGE_ID 28 413 #define VIA_ID 4 414 #endif 415 416 #if defined(CONFIG_PCI) 417 418 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 419 420 #undef CONFIG_EEPRO100 421 #undef CONFIG_TULIP 422 423 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 424 425 #endif /* CONFIG_PCI */ 426 427 428 #if defined(CONFIG_TSEC_ENET) 429 430 #define CONFIG_MII 1 /* MII PHY management */ 431 #define CONFIG_TSEC1 1 432 #define CONFIG_TSEC1_NAME "eTSEC0" 433 #define CONFIG_TSEC2 1 434 #define CONFIG_TSEC2_NAME "eTSEC1" 435 #define CONFIG_TSEC3 1 436 #define CONFIG_TSEC3_NAME "eTSEC2" 437 #define CONFIG_TSEC4 438 #define CONFIG_TSEC4_NAME "eTSEC3" 439 #undef CONFIG_MPC85XX_FEC 440 441 #define CONFIG_PHY_MARVELL 442 443 #define TSEC1_PHY_ADDR 0 444 #define TSEC2_PHY_ADDR 1 445 #define TSEC3_PHY_ADDR 2 446 #define TSEC4_PHY_ADDR 3 447 448 #define TSEC1_PHYIDX 0 449 #define TSEC2_PHYIDX 0 450 #define TSEC3_PHYIDX 0 451 #define TSEC4_PHYIDX 0 452 #define TSEC1_FLAGS TSEC_GIGABIT 453 #define TSEC2_FLAGS TSEC_GIGABIT 454 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 455 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 456 457 /* Options are: eTSEC[0-3] */ 458 #define CONFIG_ETHPRIME "eTSEC0" 459 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 460 #endif /* CONFIG_TSEC_ENET */ 461 462 /* 463 * Environment 464 */ 465 #define CONFIG_ENV_IS_IN_FLASH 1 466 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 467 #define CONFIG_ENV_ADDR 0xfff80000 468 #else 469 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 470 #endif 471 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 472 #define CONFIG_ENV_SIZE 0x2000 473 474 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 475 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 476 477 /* 478 * BOOTP options 479 */ 480 #define CONFIG_BOOTP_BOOTFILESIZE 481 #define CONFIG_BOOTP_BOOTPATH 482 #define CONFIG_BOOTP_GATEWAY 483 #define CONFIG_BOOTP_HOSTNAME 484 485 486 /* 487 * Command line configuration. 488 */ 489 #define CONFIG_CMD_PING 490 #define CONFIG_CMD_I2C 491 #define CONFIG_CMD_MII 492 #define CONFIG_CMD_IRQ 493 #define CONFIG_CMD_REGINFO 494 495 #if defined(CONFIG_PCI) 496 #define CONFIG_CMD_PCI 497 #endif 498 499 500 #undef CONFIG_WATCHDOG /* watchdog disabled */ 501 502 /* 503 * Miscellaneous configurable options 504 */ 505 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 506 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 507 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 508 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 509 #if defined(CONFIG_CMD_KGDB) 510 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 511 #else 512 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 513 #endif 514 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 515 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 516 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 517 518 /* 519 * For booting Linux, the board info and command line data 520 * have to be in the first 64 MB of memory, since this is 521 * the maximum mapped by the Linux kernel during initialization. 522 */ 523 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 524 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 525 526 #if defined(CONFIG_CMD_KGDB) 527 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 528 #endif 529 530 /* 531 * Environment Configuration 532 */ 533 #if defined(CONFIG_TSEC_ENET) 534 #define CONFIG_HAS_ETH0 535 #define CONFIG_HAS_ETH1 536 #define CONFIG_HAS_ETH2 537 #define CONFIG_HAS_ETH3 538 #endif 539 540 #define CONFIG_IPADDR 192.168.1.253 541 542 #define CONFIG_HOSTNAME unknown 543 #define CONFIG_ROOTPATH "/nfsroot" 544 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 545 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 546 547 #define CONFIG_SERVERIP 192.168.1.1 548 #define CONFIG_GATEWAYIP 192.168.1.1 549 #define CONFIG_NETMASK 255.255.255.0 550 551 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 552 553 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 554 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 555 556 #define CONFIG_BAUDRATE 115200 557 558 #define CONFIG_EXTRA_ENV_SETTINGS \ 559 "hwconfig=fsl_ddr:ecc=off\0" \ 560 "netdev=eth0\0" \ 561 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 562 "tftpflash=tftpboot $loadaddr $uboot; " \ 563 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 564 " +$filesize; " \ 565 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 566 " +$filesize; " \ 567 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 568 " $filesize; " \ 569 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 570 " +$filesize; " \ 571 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 572 " $filesize\0" \ 573 "consoledev=ttyS1\0" \ 574 "ramdiskaddr=2000000\0" \ 575 "ramdiskfile=ramdisk.uboot\0" \ 576 "fdtaddr=c00000\0" \ 577 "fdtfile=mpc8548cds.dtb\0" 578 579 #define CONFIG_NFSBOOTCOMMAND \ 580 "setenv bootargs root=/dev/nfs rw " \ 581 "nfsroot=$serverip:$rootpath " \ 582 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 583 "console=$consoledev,$baudrate $othbootargs;" \ 584 "tftp $loadaddr $bootfile;" \ 585 "tftp $fdtaddr $fdtfile;" \ 586 "bootm $loadaddr - $fdtaddr" 587 588 589 #define CONFIG_RAMBOOTCOMMAND \ 590 "setenv bootargs root=/dev/ram rw " \ 591 "console=$consoledev,$baudrate $othbootargs;" \ 592 "tftp $ramdiskaddr $ramdiskfile;" \ 593 "tftp $loadaddr $bootfile;" \ 594 "tftp $fdtaddr $fdtfile;" \ 595 "bootm $loadaddr $ramdiskaddr $fdtaddr" 596 597 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 598 599 #endif /* __CONFIG_H */ 600