1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 /* High Level Configuration Options */ 19 #define CONFIG_BOOKE 1 /* BOOKE */ 20 #define CONFIG_E500 1 /* BOOKE e500 family */ 21 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 22 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 23 24 #ifndef CONFIG_SYS_TEXT_BASE 25 #define CONFIG_SYS_TEXT_BASE 0xfff80000 26 #endif 27 28 #define CONFIG_SYS_SRIO 29 #define CONFIG_SRIO1 /* SRIO port 1 */ 30 31 #define CONFIG_PCI /* enable any pci type devices */ 32 #define CONFIG_PCI1 /* PCI controller 1 */ 33 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 34 #undef CONFIG_PCI2 35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 36 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 37 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 38 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 39 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #define CONFIG_ENV_OVERWRITE 42 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 43 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 44 45 #define CONFIG_FSL_VIA 46 47 #ifndef __ASSEMBLY__ 48 extern unsigned long get_clock_freq(void); 49 #endif 50 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 51 52 /* 53 * These can be toggled for performance analysis, otherwise use default. 54 */ 55 #define CONFIG_L2_CACHE /* toggle L2 cache */ 56 #define CONFIG_BTB /* toggle branch predition */ 57 58 /* 59 * Only possible on E500 Version 2 or newer cores. 60 */ 61 #define CONFIG_ENABLE_36BIT_PHYS 1 62 63 #ifdef CONFIG_PHYS_64BIT 64 #define CONFIG_ADDR_MAP 65 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 66 #endif 67 68 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 69 #define CONFIG_SYS_MEMTEST_END 0x00400000 70 71 #define CONFIG_SYS_CCSRBAR 0xe0000000 72 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 73 74 /* DDR Setup */ 75 #define CONFIG_SYS_FSL_DDR2 76 #undef CONFIG_FSL_DDR_INTERACTIVE 77 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 78 #define CONFIG_DDR_SPD 79 80 #define CONFIG_DDR_ECC 81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 83 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 87 #define CONFIG_NUM_DDR_CONTROLLERS 1 88 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 89 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 90 91 /* I2C addresses of SPD EEPROMs */ 92 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 93 94 /* Make sure required options are set */ 95 #ifndef CONFIG_SPD_EEPROM 96 #error ("CONFIG_SPD_EEPROM is required") 97 #endif 98 99 #undef CONFIG_CLOCKS_IN_MHZ 100 /* 101 * Physical Address Map 102 * 103 * 32bit: 104 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 105 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 106 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 107 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 108 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 109 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 110 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 111 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 112 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 113 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 114 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 115 * 116 * 36bit: 117 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 118 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 119 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 120 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 121 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 122 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 123 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 124 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 125 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 126 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 127 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 128 * 129 */ 130 131 /* 132 * Local Bus Definitions 133 */ 134 135 /* 136 * FLASH on the Local Bus 137 * Two banks, 8M each, using the CFI driver. 138 * Boot from BR0/OR0 bank at 0xff00_0000 139 * Alternate BR1/OR1 bank at 0xff80_0000 140 * 141 * BR0, BR1: 142 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 143 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 144 * Port Size = 16 bits = BRx[19:20] = 10 145 * Use GPCM = BRx[24:26] = 000 146 * Valid = BRx[31] = 1 147 * 148 * 0 4 8 12 16 20 24 28 149 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 150 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 151 * 152 * OR0, OR1: 153 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 154 * Reserved ORx[17:18] = 11, confusion here? 155 * CSNT = ORx[20] = 1 156 * ACS = half cycle delay = ORx[21:22] = 11 157 * SCY = 6 = ORx[24:27] = 0110 158 * TRLX = use relaxed timing = ORx[29] = 1 159 * EAD = use external address latch delay = OR[31] = 1 160 * 161 * 0 4 8 12 16 20 24 28 162 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 163 */ 164 165 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 166 #ifdef CONFIG_PHYS_64BIT 167 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 168 #else 169 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 170 #endif 171 172 #define CONFIG_SYS_BR0_PRELIM \ 173 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 174 #define CONFIG_SYS_BR1_PRELIM \ 175 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 176 177 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 178 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 179 180 #define CONFIG_SYS_FLASH_BANKS_LIST \ 181 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 182 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 183 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 184 #undef CONFIG_SYS_FLASH_CHECKSUM 185 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 186 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 187 188 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 189 190 #define CONFIG_FLASH_CFI_DRIVER 191 #define CONFIG_SYS_FLASH_CFI 192 #define CONFIG_SYS_FLASH_EMPTY_INFO 193 194 #define CONFIG_HWCONFIG /* enable hwconfig */ 195 196 /* 197 * SDRAM on the Local Bus 198 */ 199 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 200 #ifdef CONFIG_PHYS_64BIT 201 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 202 #else 203 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 204 #endif 205 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 206 207 /* 208 * Base Register 2 and Option Register 2 configure SDRAM. 209 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 210 * 211 * For BR2, need: 212 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 213 * port-size = 32-bits = BR2[19:20] = 11 214 * no parity checking = BR2[21:22] = 00 215 * SDRAM for MSEL = BR2[24:26] = 011 216 * Valid = BR[31] = 1 217 * 218 * 0 4 8 12 16 20 24 28 219 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 220 * 221 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 222 * FIXME: the top 17 bits of BR2. 223 */ 224 225 #define CONFIG_SYS_BR2_PRELIM \ 226 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 227 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 228 229 /* 230 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 231 * 232 * For OR2, need: 233 * 64MB mask for AM, OR2[0:7] = 1111 1100 234 * XAM, OR2[17:18] = 11 235 * 9 columns OR2[19-21] = 010 236 * 13 rows OR2[23-25] = 100 237 * EAD set for extra time OR[31] = 1 238 * 239 * 0 4 8 12 16 20 24 28 240 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 241 */ 242 243 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 244 245 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 246 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 247 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 248 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 249 250 /* 251 * Common settings for all Local Bus SDRAM commands. 252 * At run time, either BSMA1516 (for CPU 1.1) 253 * or BSMA1617 (for CPU 1.0) (old) 254 * is OR'ed in too. 255 */ 256 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 257 | LSDMR_PRETOACT7 \ 258 | LSDMR_ACTTORW7 \ 259 | LSDMR_BL8 \ 260 | LSDMR_WRC4 \ 261 | LSDMR_CL3 \ 262 | LSDMR_RFEN \ 263 ) 264 265 /* 266 * The CADMUS registers are connected to CS3 on CDS. 267 * The new memory map places CADMUS at 0xf8000000. 268 * 269 * For BR3, need: 270 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 271 * port-size = 8-bits = BR[19:20] = 01 272 * no parity checking = BR[21:22] = 00 273 * GPMC for MSEL = BR[24:26] = 000 274 * Valid = BR[31] = 1 275 * 276 * 0 4 8 12 16 20 24 28 277 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 278 * 279 * For OR3, need: 280 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 281 * disable buffer ctrl OR[19] = 0 282 * CSNT OR[20] = 1 283 * ACS OR[21:22] = 11 284 * XACS OR[23] = 1 285 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 286 * SETA OR[28] = 0 287 * TRLX OR[29] = 1 288 * EHTR OR[30] = 1 289 * EAD extra time OR[31] = 1 290 * 291 * 0 4 8 12 16 20 24 28 292 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 293 */ 294 295 #define CONFIG_FSL_CADMUS 296 297 #define CADMUS_BASE_ADDR 0xf8000000 298 #ifdef CONFIG_PHYS_64BIT 299 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 300 #else 301 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 302 #endif 303 #define CONFIG_SYS_BR3_PRELIM \ 304 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 305 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 306 307 #define CONFIG_SYS_INIT_RAM_LOCK 1 308 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 309 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 310 311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 312 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 313 314 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 315 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 316 317 /* Serial Port */ 318 #define CONFIG_CONS_INDEX 2 319 #define CONFIG_SYS_NS16550_SERIAL 320 #define CONFIG_SYS_NS16550_REG_SIZE 1 321 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 322 323 #define CONFIG_SYS_BAUDRATE_TABLE \ 324 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 325 326 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 327 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 328 329 /* 330 * I2C 331 */ 332 #define CONFIG_SYS_I2C 333 #define CONFIG_SYS_I2C_FSL 334 #define CONFIG_SYS_FSL_I2C_SPEED 400000 335 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 336 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 337 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 338 339 /* EEPROM */ 340 #define CONFIG_ID_EEPROM 341 #define CONFIG_SYS_I2C_EEPROM_CCID 342 #define CONFIG_SYS_ID_EEPROM 343 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 344 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 345 346 /* 347 * General PCI 348 * Memory space is mapped 1-1, but I/O space must start from 0. 349 */ 350 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 351 #ifdef CONFIG_PHYS_64BIT 352 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 353 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 354 #else 355 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 356 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 357 #endif 358 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 359 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 360 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 361 #ifdef CONFIG_PHYS_64BIT 362 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 363 #else 364 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 365 #endif 366 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 367 368 #ifdef CONFIG_PCIE1 369 #define CONFIG_SYS_PCIE1_NAME "Slot" 370 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 373 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 374 #else 375 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 376 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 377 #endif 378 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 379 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 380 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 381 #ifdef CONFIG_PHYS_64BIT 382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 383 #else 384 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 385 #endif 386 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 387 #endif 388 389 /* 390 * RapidIO MMU 391 */ 392 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 393 #ifdef CONFIG_PHYS_64BIT 394 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 395 #else 396 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 397 #endif 398 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 399 400 #ifdef CONFIG_LEGACY 401 #define BRIDGE_ID 17 402 #define VIA_ID 2 403 #else 404 #define BRIDGE_ID 28 405 #define VIA_ID 4 406 #endif 407 408 #if defined(CONFIG_PCI) 409 410 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 411 412 #undef CONFIG_EEPRO100 413 #undef CONFIG_TULIP 414 415 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 416 417 #endif /* CONFIG_PCI */ 418 419 #if defined(CONFIG_TSEC_ENET) 420 421 #define CONFIG_MII 1 /* MII PHY management */ 422 #define CONFIG_TSEC1 1 423 #define CONFIG_TSEC1_NAME "eTSEC0" 424 #define CONFIG_TSEC2 1 425 #define CONFIG_TSEC2_NAME "eTSEC1" 426 #define CONFIG_TSEC3 1 427 #define CONFIG_TSEC3_NAME "eTSEC2" 428 #define CONFIG_TSEC4 429 #define CONFIG_TSEC4_NAME "eTSEC3" 430 #undef CONFIG_MPC85XX_FEC 431 432 #define CONFIG_PHY_MARVELL 433 434 #define TSEC1_PHY_ADDR 0 435 #define TSEC2_PHY_ADDR 1 436 #define TSEC3_PHY_ADDR 2 437 #define TSEC4_PHY_ADDR 3 438 439 #define TSEC1_PHYIDX 0 440 #define TSEC2_PHYIDX 0 441 #define TSEC3_PHYIDX 0 442 #define TSEC4_PHYIDX 0 443 #define TSEC1_FLAGS TSEC_GIGABIT 444 #define TSEC2_FLAGS TSEC_GIGABIT 445 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 446 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 447 448 /* Options are: eTSEC[0-3] */ 449 #define CONFIG_ETHPRIME "eTSEC0" 450 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 451 #endif /* CONFIG_TSEC_ENET */ 452 453 /* 454 * Environment 455 */ 456 #define CONFIG_ENV_IS_IN_FLASH 1 457 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 458 #define CONFIG_ENV_ADDR 0xfff80000 459 #else 460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 461 #endif 462 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 463 #define CONFIG_ENV_SIZE 0x2000 464 465 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 466 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 467 468 /* 469 * BOOTP options 470 */ 471 #define CONFIG_BOOTP_BOOTFILESIZE 472 #define CONFIG_BOOTP_BOOTPATH 473 #define CONFIG_BOOTP_GATEWAY 474 #define CONFIG_BOOTP_HOSTNAME 475 476 /* 477 * Command line configuration. 478 */ 479 #define CONFIG_CMD_IRQ 480 #define CONFIG_CMD_REGINFO 481 482 #if defined(CONFIG_PCI) 483 #define CONFIG_CMD_PCI 484 #endif 485 486 #undef CONFIG_WATCHDOG /* watchdog disabled */ 487 488 /* 489 * Miscellaneous configurable options 490 */ 491 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 492 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 493 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 494 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 495 #if defined(CONFIG_CMD_KGDB) 496 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 497 #else 498 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 499 #endif 500 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 501 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 502 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 503 504 /* 505 * For booting Linux, the board info and command line data 506 * have to be in the first 64 MB of memory, since this is 507 * the maximum mapped by the Linux kernel during initialization. 508 */ 509 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 510 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 511 512 #if defined(CONFIG_CMD_KGDB) 513 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 514 #endif 515 516 /* 517 * Environment Configuration 518 */ 519 #if defined(CONFIG_TSEC_ENET) 520 #define CONFIG_HAS_ETH0 521 #define CONFIG_HAS_ETH1 522 #define CONFIG_HAS_ETH2 523 #define CONFIG_HAS_ETH3 524 #endif 525 526 #define CONFIG_IPADDR 192.168.1.253 527 528 #define CONFIG_HOSTNAME unknown 529 #define CONFIG_ROOTPATH "/nfsroot" 530 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 531 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 532 533 #define CONFIG_SERVERIP 192.168.1.1 534 #define CONFIG_GATEWAYIP 192.168.1.1 535 #define CONFIG_NETMASK 255.255.255.0 536 537 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 538 539 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 540 541 #define CONFIG_BAUDRATE 115200 542 543 #define CONFIG_EXTRA_ENV_SETTINGS \ 544 "hwconfig=fsl_ddr:ecc=off\0" \ 545 "netdev=eth0\0" \ 546 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 547 "tftpflash=tftpboot $loadaddr $uboot; " \ 548 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 549 " +$filesize; " \ 550 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 551 " +$filesize; " \ 552 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 553 " $filesize; " \ 554 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 555 " +$filesize; " \ 556 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 557 " $filesize\0" \ 558 "consoledev=ttyS1\0" \ 559 "ramdiskaddr=2000000\0" \ 560 "ramdiskfile=ramdisk.uboot\0" \ 561 "fdtaddr=1e00000\0" \ 562 "fdtfile=mpc8548cds.dtb\0" 563 564 #define CONFIG_NFSBOOTCOMMAND \ 565 "setenv bootargs root=/dev/nfs rw " \ 566 "nfsroot=$serverip:$rootpath " \ 567 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 568 "console=$consoledev,$baudrate $othbootargs;" \ 569 "tftp $loadaddr $bootfile;" \ 570 "tftp $fdtaddr $fdtfile;" \ 571 "bootm $loadaddr - $fdtaddr" 572 573 #define CONFIG_RAMBOOTCOMMAND \ 574 "setenv bootargs root=/dev/ram rw " \ 575 "console=$consoledev,$baudrate $othbootargs;" \ 576 "tftp $ramdiskaddr $ramdiskfile;" \ 577 "tftp $loadaddr $bootfile;" \ 578 "tftp $fdtaddr $fdtfile;" \ 579 "bootm $loadaddr $ramdiskaddr $fdtaddr" 580 581 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 582 583 #endif /* __CONFIG_H */ 584