1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8548cds board configuration file 25 * 26 * Please refer to doc/README.mpc85xxcds for more info. 27 * 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* High Level Configuration Options */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 37 #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xfff80000 41 #endif 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 46 #define CONFIG_PCI /* enable any pci type devices */ 47 #define CONFIG_PCI1 /* PCI controller 1 */ 48 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 49 #undef CONFIG_PCI2 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 58 59 #define CONFIG_FSL_VIA 60 61 #ifndef __ASSEMBLY__ 62 extern unsigned long get_clock_freq(void); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 88 89 /* DDR Setup */ 90 #define CONFIG_FSL_DDR2 91 #undef CONFIG_FSL_DDR_INTERACTIVE 92 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 93 #define CONFIG_DDR_SPD 94 95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 96 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 97 98 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 99 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 100 101 #define CONFIG_NUM_DDR_CONTROLLERS 1 102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 103 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 104 105 /* I2C addresses of SPD EEPROMs */ 106 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 107 108 /* Make sure required options are set */ 109 #ifndef CONFIG_SPD_EEPROM 110 #error ("CONFIG_SPD_EEPROM is required") 111 #endif 112 113 #undef CONFIG_CLOCKS_IN_MHZ 114 115 /* 116 * Local Bus Definitions 117 */ 118 119 /* 120 * FLASH on the Local Bus 121 * Two banks, 8M each, using the CFI driver. 122 * Boot from BR0/OR0 bank at 0xff00_0000 123 * Alternate BR1/OR1 bank at 0xff80_0000 124 * 125 * BR0, BR1: 126 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 127 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 128 * Port Size = 16 bits = BRx[19:20] = 10 129 * Use GPCM = BRx[24:26] = 000 130 * Valid = BRx[31] = 1 131 * 132 * 0 4 8 12 16 20 24 28 133 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 134 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 135 * 136 * OR0, OR1: 137 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 138 * Reserved ORx[17:18] = 11, confusion here? 139 * CSNT = ORx[20] = 1 140 * ACS = half cycle delay = ORx[21:22] = 11 141 * SCY = 6 = ORx[24:27] = 0110 142 * TRLX = use relaxed timing = ORx[29] = 1 143 * EAD = use external address latch delay = OR[31] = 1 144 * 145 * 0 4 8 12 16 20 24 28 146 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 147 */ 148 149 #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ 150 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 151 152 #define CONFIG_SYS_BR0_PRELIM 0xff801001 153 #define CONFIG_SYS_BR1_PRELIM 0xff001001 154 155 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 156 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 157 158 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 159 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 160 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 161 #undef CONFIG_SYS_FLASH_CHECKSUM 162 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 163 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 164 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 166 167 #define CONFIG_FLASH_CFI_DRIVER 168 #define CONFIG_SYS_FLASH_CFI 169 #define CONFIG_SYS_FLASH_EMPTY_INFO 170 171 172 /* 173 * SDRAM on the Local Bus 174 */ 175 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 176 #define CONFIG_SYS_LBC_CACHE_SIZE 64 177 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ 178 #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 179 180 #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ 181 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 182 183 /* 184 * Base Register 2 and Option Register 2 configure SDRAM. 185 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 186 * 187 * For BR2, need: 188 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 189 * port-size = 32-bits = BR2[19:20] = 11 190 * no parity checking = BR2[21:22] = 00 191 * SDRAM for MSEL = BR2[24:26] = 011 192 * Valid = BR[31] = 1 193 * 194 * 0 4 8 12 16 20 24 28 195 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 196 * 197 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 198 * FIXME: the top 17 bits of BR2. 199 */ 200 201 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 202 203 /* 204 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 205 * 206 * For OR2, need: 207 * 64MB mask for AM, OR2[0:7] = 1111 1100 208 * XAM, OR2[17:18] = 11 209 * 9 columns OR2[19-21] = 010 210 * 13 rows OR2[23-25] = 100 211 * EAD set for extra time OR[31] = 1 212 * 213 * 0 4 8 12 16 20 24 28 214 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 215 */ 216 217 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 218 219 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 220 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 221 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 222 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 223 224 /* 225 * Common settings for all Local Bus SDRAM commands. 226 * At run time, either BSMA1516 (for CPU 1.1) 227 * or BSMA1617 (for CPU 1.0) (old) 228 * is OR'ed in too. 229 */ 230 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 231 | LSDMR_PRETOACT7 \ 232 | LSDMR_ACTTORW7 \ 233 | LSDMR_BL8 \ 234 | LSDMR_WRC4 \ 235 | LSDMR_CL3 \ 236 | LSDMR_RFEN \ 237 ) 238 239 /* 240 * The CADMUS registers are connected to CS3 on CDS. 241 * The new memory map places CADMUS at 0xf8000000. 242 * 243 * For BR3, need: 244 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 245 * port-size = 8-bits = BR[19:20] = 01 246 * no parity checking = BR[21:22] = 00 247 * GPMC for MSEL = BR[24:26] = 000 248 * Valid = BR[31] = 1 249 * 250 * 0 4 8 12 16 20 24 28 251 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 252 * 253 * For OR3, need: 254 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 255 * disable buffer ctrl OR[19] = 0 256 * CSNT OR[20] = 1 257 * ACS OR[21:22] = 11 258 * XACS OR[23] = 1 259 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 260 * SETA OR[28] = 0 261 * TRLX OR[29] = 1 262 * EHTR OR[30] = 1 263 * EAD extra time OR[31] = 1 264 * 265 * 0 4 8 12 16 20 24 28 266 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 267 */ 268 269 #define CONFIG_FSL_CADMUS 270 271 #define CADMUS_BASE_ADDR 0xf8000000 272 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 273 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 274 275 #define CONFIG_SYS_INIT_RAM_LOCK 1 276 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 277 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 278 279 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 280 281 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 282 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 283 284 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 285 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 286 287 /* Serial Port */ 288 #define CONFIG_CONS_INDEX 2 289 #define CONFIG_SYS_NS16550 290 #define CONFIG_SYS_NS16550_SERIAL 291 #define CONFIG_SYS_NS16550_REG_SIZE 1 292 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 293 294 #define CONFIG_SYS_BAUDRATE_TABLE \ 295 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 296 297 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 298 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 299 300 /* Use the HUSH parser */ 301 #define CONFIG_SYS_HUSH_PARSER 302 #ifdef CONFIG_SYS_HUSH_PARSER 303 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 304 #endif 305 306 /* pass open firmware flat tree */ 307 #define CONFIG_OF_LIBFDT 1 308 #define CONFIG_OF_BOARD_SETUP 1 309 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 310 311 /* 312 * I2C 313 */ 314 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 315 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 316 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 317 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 318 #define CONFIG_SYS_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 320 #define CONFIG_SYS_I2C_OFFSET 0x3000 321 322 /* EEPROM */ 323 #define CONFIG_ID_EEPROM 324 #define CONFIG_SYS_I2C_EEPROM_CCID 325 #define CONFIG_SYS_ID_EEPROM 326 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 328 329 /* 330 * General PCI 331 * Memory space is mapped 1-1, but I/O space must start from 0. 332 */ 333 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 334 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 335 336 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 337 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 338 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 339 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 340 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 341 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 342 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 343 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 344 345 #ifdef CONFIG_PCI2 346 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 347 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 348 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 349 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 350 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 351 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 352 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 353 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 354 #endif 355 356 #ifdef CONFIG_PCIE1 357 #define CONFIG_SYS_PCIE1_NAME "Slot" 358 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 359 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 360 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 361 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 362 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 363 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 364 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 365 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 366 #endif 367 368 /* 369 * RapidIO MMU 370 */ 371 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 372 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 373 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 374 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 375 376 #ifdef CONFIG_LEGACY 377 #define BRIDGE_ID 17 378 #define VIA_ID 2 379 #else 380 #define BRIDGE_ID 28 381 #define VIA_ID 4 382 #endif 383 384 #if defined(CONFIG_PCI) 385 386 #define CONFIG_NET_MULTI 387 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 388 389 #undef CONFIG_EEPRO100 390 #undef CONFIG_TULIP 391 392 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 393 394 #endif /* CONFIG_PCI */ 395 396 397 #if defined(CONFIG_TSEC_ENET) 398 399 #ifndef CONFIG_NET_MULTI 400 #define CONFIG_NET_MULTI 1 401 #endif 402 403 #define CONFIG_MII 1 /* MII PHY management */ 404 #define CONFIG_TSEC1 1 405 #define CONFIG_TSEC1_NAME "eTSEC0" 406 #define CONFIG_TSEC2 1 407 #define CONFIG_TSEC2_NAME "eTSEC1" 408 #define CONFIG_TSEC3 1 409 #define CONFIG_TSEC3_NAME "eTSEC2" 410 #define CONFIG_TSEC4 411 #define CONFIG_TSEC4_NAME "eTSEC3" 412 #undef CONFIG_MPC85XX_FEC 413 414 #define TSEC1_PHY_ADDR 0 415 #define TSEC2_PHY_ADDR 1 416 #define TSEC3_PHY_ADDR 2 417 #define TSEC4_PHY_ADDR 3 418 419 #define TSEC1_PHYIDX 0 420 #define TSEC2_PHYIDX 0 421 #define TSEC3_PHYIDX 0 422 #define TSEC4_PHYIDX 0 423 #define TSEC1_FLAGS TSEC_GIGABIT 424 #define TSEC2_FLAGS TSEC_GIGABIT 425 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 426 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427 428 /* Options are: eTSEC[0-3] */ 429 #define CONFIG_ETHPRIME "eTSEC0" 430 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 431 #endif /* CONFIG_TSEC_ENET */ 432 433 /* 434 * Environment 435 */ 436 #define CONFIG_ENV_IS_IN_FLASH 1 437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 438 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 439 #define CONFIG_ENV_SIZE 0x2000 440 441 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 442 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 443 444 /* 445 * BOOTP options 446 */ 447 #define CONFIG_BOOTP_BOOTFILESIZE 448 #define CONFIG_BOOTP_BOOTPATH 449 #define CONFIG_BOOTP_GATEWAY 450 #define CONFIG_BOOTP_HOSTNAME 451 452 453 /* 454 * Command line configuration. 455 */ 456 #include <config_cmd_default.h> 457 458 #define CONFIG_CMD_PING 459 #define CONFIG_CMD_I2C 460 #define CONFIG_CMD_MII 461 #define CONFIG_CMD_ELF 462 #define CONFIG_CMD_IRQ 463 #define CONFIG_CMD_SETEXPR 464 #define CONFIG_CMD_REGINFO 465 466 #if defined(CONFIG_PCI) 467 #define CONFIG_CMD_PCI 468 #endif 469 470 471 #undef CONFIG_WATCHDOG /* watchdog disabled */ 472 473 /* 474 * Miscellaneous configurable options 475 */ 476 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 477 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 478 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 479 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 480 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 481 #if defined(CONFIG_CMD_KGDB) 482 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 483 #else 484 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 485 #endif 486 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 487 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 488 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 489 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 490 491 /* 492 * For booting Linux, the board info and command line data 493 * have to be in the first 64 MB of memory, since this is 494 * the maximum mapped by the Linux kernel during initialization. 495 */ 496 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 497 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 498 499 #if defined(CONFIG_CMD_KGDB) 500 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 501 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 502 #endif 503 504 /* 505 * Environment Configuration 506 */ 507 508 /* The mac addresses for all ethernet interface */ 509 #if defined(CONFIG_TSEC_ENET) 510 #define CONFIG_HAS_ETH0 511 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 512 #define CONFIG_HAS_ETH1 513 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 514 #define CONFIG_HAS_ETH2 515 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 516 #define CONFIG_HAS_ETH3 517 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 518 #endif 519 520 #define CONFIG_IPADDR 192.168.1.253 521 522 #define CONFIG_HOSTNAME unknown 523 #define CONFIG_ROOTPATH /nfsroot 524 #define CONFIG_BOOTFILE 8548cds/uImage.uboot 525 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 526 527 #define CONFIG_SERVERIP 192.168.1.1 528 #define CONFIG_GATEWAYIP 192.168.1.1 529 #define CONFIG_NETMASK 255.255.255.0 530 531 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 532 533 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 534 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 535 536 #define CONFIG_BAUDRATE 115200 537 538 #define CONFIG_EXTRA_ENV_SETTINGS \ 539 "netdev=eth0\0" \ 540 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 541 "tftpflash=tftpboot $loadaddr $uboot; " \ 542 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 543 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 544 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 545 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 546 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 547 "consoledev=ttyS1\0" \ 548 "ramdiskaddr=2000000\0" \ 549 "ramdiskfile=ramdisk.uboot\0" \ 550 "fdtaddr=c00000\0" \ 551 "fdtfile=mpc8548cds.dtb\0" 552 553 #define CONFIG_NFSBOOTCOMMAND \ 554 "setenv bootargs root=/dev/nfs rw " \ 555 "nfsroot=$serverip:$rootpath " \ 556 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 557 "console=$consoledev,$baudrate $othbootargs;" \ 558 "tftp $loadaddr $bootfile;" \ 559 "tftp $fdtaddr $fdtfile;" \ 560 "bootm $loadaddr - $fdtaddr" 561 562 563 #define CONFIG_RAMBOOTCOMMAND \ 564 "setenv bootargs root=/dev/ram rw " \ 565 "console=$consoledev,$baudrate $othbootargs;" \ 566 "tftp $ramdiskaddr $ramdiskfile;" \ 567 "tftp $loadaddr $bootfile;" \ 568 "tftp $fdtaddr $fdtfile;" \ 569 "bootm $loadaddr $ramdiskaddr $fdtaddr" 570 571 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 572 573 #endif /* __CONFIG_H */ 574