1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_SYS_SRIO 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 19 #define CONFIG_PCI1 /* PCI controller 1 */ 20 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 21 #undef CONFIG_PCI2 22 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 23 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 24 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 26 27 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 28 #define CONFIG_ENV_OVERWRITE 29 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 30 31 #define CONFIG_FSL_VIA 32 33 #ifndef __ASSEMBLY__ 34 extern unsigned long get_clock_freq(void); 35 #endif 36 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 37 38 /* 39 * These can be toggled for performance analysis, otherwise use default. 40 */ 41 #define CONFIG_L2_CACHE /* toggle L2 cache */ 42 #define CONFIG_BTB /* toggle branch predition */ 43 44 /* 45 * Only possible on E500 Version 2 or newer cores. 46 */ 47 #define CONFIG_ENABLE_36BIT_PHYS 1 48 49 #ifdef CONFIG_PHYS_64BIT 50 #define CONFIG_ADDR_MAP 51 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 52 #endif 53 54 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 55 #define CONFIG_SYS_MEMTEST_END 0x00400000 56 57 #define CONFIG_SYS_CCSRBAR 0xe0000000 58 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 59 60 /* DDR Setup */ 61 #undef CONFIG_FSL_DDR_INTERACTIVE 62 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 63 #define CONFIG_DDR_SPD 64 65 #define CONFIG_DDR_ECC 66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 67 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 68 69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 71 72 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 73 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 74 75 /* I2C addresses of SPD EEPROMs */ 76 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 77 78 /* Make sure required options are set */ 79 #ifndef CONFIG_SPD_EEPROM 80 #error ("CONFIG_SPD_EEPROM is required") 81 #endif 82 83 #undef CONFIG_CLOCKS_IN_MHZ 84 /* 85 * Physical Address Map 86 * 87 * 32bit: 88 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 89 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 90 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 91 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 92 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 93 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 94 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 95 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 96 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 97 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 98 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 99 * 100 * 36bit: 101 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 102 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 103 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 104 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 105 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 106 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 107 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 108 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 109 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 110 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 111 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 112 * 113 */ 114 115 /* 116 * Local Bus Definitions 117 */ 118 119 /* 120 * FLASH on the Local Bus 121 * Two banks, 8M each, using the CFI driver. 122 * Boot from BR0/OR0 bank at 0xff00_0000 123 * Alternate BR1/OR1 bank at 0xff80_0000 124 * 125 * BR0, BR1: 126 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 127 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 128 * Port Size = 16 bits = BRx[19:20] = 10 129 * Use GPCM = BRx[24:26] = 000 130 * Valid = BRx[31] = 1 131 * 132 * 0 4 8 12 16 20 24 28 133 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 134 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 135 * 136 * OR0, OR1: 137 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 138 * Reserved ORx[17:18] = 11, confusion here? 139 * CSNT = ORx[20] = 1 140 * ACS = half cycle delay = ORx[21:22] = 11 141 * SCY = 6 = ORx[24:27] = 0110 142 * TRLX = use relaxed timing = ORx[29] = 1 143 * EAD = use external address latch delay = OR[31] = 1 144 * 145 * 0 4 8 12 16 20 24 28 146 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 147 */ 148 149 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 150 #ifdef CONFIG_PHYS_64BIT 151 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 152 #else 153 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 154 #endif 155 156 #define CONFIG_SYS_BR0_PRELIM \ 157 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 158 #define CONFIG_SYS_BR1_PRELIM \ 159 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 160 161 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 162 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 163 164 #define CONFIG_SYS_FLASH_BANKS_LIST \ 165 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 166 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 167 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 168 #undef CONFIG_SYS_FLASH_CHECKSUM 169 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 170 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 171 172 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 173 174 #define CONFIG_FLASH_CFI_DRIVER 175 #define CONFIG_SYS_FLASH_CFI 176 #define CONFIG_SYS_FLASH_EMPTY_INFO 177 178 #define CONFIG_HWCONFIG /* enable hwconfig */ 179 180 /* 181 * SDRAM on the Local Bus 182 */ 183 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 186 #else 187 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 188 #endif 189 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 190 191 /* 192 * Base Register 2 and Option Register 2 configure SDRAM. 193 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 194 * 195 * For BR2, need: 196 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 197 * port-size = 32-bits = BR2[19:20] = 11 198 * no parity checking = BR2[21:22] = 00 199 * SDRAM for MSEL = BR2[24:26] = 011 200 * Valid = BR[31] = 1 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 204 * 205 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 206 * FIXME: the top 17 bits of BR2. 207 */ 208 209 #define CONFIG_SYS_BR2_PRELIM \ 210 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 211 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 212 213 /* 214 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 215 * 216 * For OR2, need: 217 * 64MB mask for AM, OR2[0:7] = 1111 1100 218 * XAM, OR2[17:18] = 11 219 * 9 columns OR2[19-21] = 010 220 * 13 rows OR2[23-25] = 100 221 * EAD set for extra time OR[31] = 1 222 * 223 * 0 4 8 12 16 20 24 28 224 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 225 */ 226 227 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 228 229 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 230 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 231 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 232 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 233 234 /* 235 * Common settings for all Local Bus SDRAM commands. 236 * At run time, either BSMA1516 (for CPU 1.1) 237 * or BSMA1617 (for CPU 1.0) (old) 238 * is OR'ed in too. 239 */ 240 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 241 | LSDMR_PRETOACT7 \ 242 | LSDMR_ACTTORW7 \ 243 | LSDMR_BL8 \ 244 | LSDMR_WRC4 \ 245 | LSDMR_CL3 \ 246 | LSDMR_RFEN \ 247 ) 248 249 /* 250 * The CADMUS registers are connected to CS3 on CDS. 251 * The new memory map places CADMUS at 0xf8000000. 252 * 253 * For BR3, need: 254 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 255 * port-size = 8-bits = BR[19:20] = 01 256 * no parity checking = BR[21:22] = 00 257 * GPMC for MSEL = BR[24:26] = 000 258 * Valid = BR[31] = 1 259 * 260 * 0 4 8 12 16 20 24 28 261 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 262 * 263 * For OR3, need: 264 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 265 * disable buffer ctrl OR[19] = 0 266 * CSNT OR[20] = 1 267 * ACS OR[21:22] = 11 268 * XACS OR[23] = 1 269 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 270 * SETA OR[28] = 0 271 * TRLX OR[29] = 1 272 * EHTR OR[30] = 1 273 * EAD extra time OR[31] = 1 274 * 275 * 0 4 8 12 16 20 24 28 276 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 277 */ 278 279 #define CONFIG_FSL_CADMUS 280 281 #define CADMUS_BASE_ADDR 0xf8000000 282 #ifdef CONFIG_PHYS_64BIT 283 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 284 #else 285 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 286 #endif 287 #define CONFIG_SYS_BR3_PRELIM \ 288 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 289 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 290 291 #define CONFIG_SYS_INIT_RAM_LOCK 1 292 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 293 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 294 295 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 296 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 297 298 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 299 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 300 301 /* Serial Port */ 302 #define CONFIG_SYS_NS16550_SERIAL 303 #define CONFIG_SYS_NS16550_REG_SIZE 1 304 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 305 306 #define CONFIG_SYS_BAUDRATE_TABLE \ 307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 308 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 311 312 /* 313 * I2C 314 */ 315 #define CONFIG_SYS_I2C 316 #define CONFIG_SYS_I2C_FSL 317 #define CONFIG_SYS_FSL_I2C_SPEED 400000 318 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 320 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 321 322 /* EEPROM */ 323 #define CONFIG_ID_EEPROM 324 #define CONFIG_SYS_I2C_EEPROM_CCID 325 #define CONFIG_SYS_ID_EEPROM 326 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 328 329 /* 330 * General PCI 331 * Memory space is mapped 1-1, but I/O space must start from 0. 332 */ 333 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 334 #ifdef CONFIG_PHYS_64BIT 335 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 336 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 337 #else 338 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 339 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 340 #endif 341 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 342 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 343 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 344 #ifdef CONFIG_PHYS_64BIT 345 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 346 #else 347 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 348 #endif 349 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 350 351 #ifdef CONFIG_PCIE1 352 #define CONFIG_SYS_PCIE1_NAME "Slot" 353 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 354 #ifdef CONFIG_PHYS_64BIT 355 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 356 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 357 #else 358 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 359 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 360 #endif 361 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 362 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 363 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 364 #ifdef CONFIG_PHYS_64BIT 365 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 366 #else 367 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 368 #endif 369 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 370 #endif 371 372 /* 373 * RapidIO MMU 374 */ 375 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 376 #ifdef CONFIG_PHYS_64BIT 377 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 378 #else 379 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 380 #endif 381 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 382 383 #ifdef CONFIG_LEGACY 384 #define BRIDGE_ID 17 385 #define VIA_ID 2 386 #else 387 #define BRIDGE_ID 28 388 #define VIA_ID 4 389 #endif 390 391 #if defined(CONFIG_PCI) 392 #undef CONFIG_EEPRO100 393 #undef CONFIG_TULIP 394 395 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 396 397 #endif /* CONFIG_PCI */ 398 399 #if defined(CONFIG_TSEC_ENET) 400 401 #define CONFIG_MII 1 /* MII PHY management */ 402 #define CONFIG_TSEC1 1 403 #define CONFIG_TSEC1_NAME "eTSEC0" 404 #define CONFIG_TSEC2 1 405 #define CONFIG_TSEC2_NAME "eTSEC1" 406 #define CONFIG_TSEC3 1 407 #define CONFIG_TSEC3_NAME "eTSEC2" 408 #define CONFIG_TSEC4 409 #define CONFIG_TSEC4_NAME "eTSEC3" 410 #undef CONFIG_MPC85XX_FEC 411 412 #define CONFIG_PHY_MARVELL 413 414 #define TSEC1_PHY_ADDR 0 415 #define TSEC2_PHY_ADDR 1 416 #define TSEC3_PHY_ADDR 2 417 #define TSEC4_PHY_ADDR 3 418 419 #define TSEC1_PHYIDX 0 420 #define TSEC2_PHYIDX 0 421 #define TSEC3_PHYIDX 0 422 #define TSEC4_PHYIDX 0 423 #define TSEC1_FLAGS TSEC_GIGABIT 424 #define TSEC2_FLAGS TSEC_GIGABIT 425 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 426 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427 428 /* Options are: eTSEC[0-3] */ 429 #define CONFIG_ETHPRIME "eTSEC0" 430 #endif /* CONFIG_TSEC_ENET */ 431 432 /* 433 * Environment 434 */ 435 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 436 #define CONFIG_ENV_ADDR 0xfff80000 437 #else 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 439 #endif 440 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 441 #define CONFIG_ENV_SIZE 0x2000 442 443 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 444 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 445 446 /* 447 * BOOTP options 448 */ 449 #define CONFIG_BOOTP_BOOTFILESIZE 450 451 #undef CONFIG_WATCHDOG /* watchdog disabled */ 452 453 /* 454 * Miscellaneous configurable options 455 */ 456 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 457 458 /* 459 * For booting Linux, the board info and command line data 460 * have to be in the first 64 MB of memory, since this is 461 * the maximum mapped by the Linux kernel during initialization. 462 */ 463 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 464 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 465 466 #if defined(CONFIG_CMD_KGDB) 467 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 468 #endif 469 470 /* 471 * Environment Configuration 472 */ 473 #if defined(CONFIG_TSEC_ENET) 474 #define CONFIG_HAS_ETH0 475 #define CONFIG_HAS_ETH1 476 #define CONFIG_HAS_ETH2 477 #define CONFIG_HAS_ETH3 478 #endif 479 480 #define CONFIG_IPADDR 192.168.1.253 481 482 #define CONFIG_HOSTNAME unknown 483 #define CONFIG_ROOTPATH "/nfsroot" 484 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 485 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 486 487 #define CONFIG_SERVERIP 192.168.1.1 488 #define CONFIG_GATEWAYIP 192.168.1.1 489 #define CONFIG_NETMASK 255.255.255.0 490 491 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 492 493 #define CONFIG_EXTRA_ENV_SETTINGS \ 494 "hwconfig=fsl_ddr:ecc=off\0" \ 495 "netdev=eth0\0" \ 496 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 497 "tftpflash=tftpboot $loadaddr $uboot; " \ 498 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 499 " +$filesize; " \ 500 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 501 " +$filesize; " \ 502 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 503 " $filesize; " \ 504 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 505 " +$filesize; " \ 506 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 507 " $filesize\0" \ 508 "consoledev=ttyS1\0" \ 509 "ramdiskaddr=2000000\0" \ 510 "ramdiskfile=ramdisk.uboot\0" \ 511 "fdtaddr=1e00000\0" \ 512 "fdtfile=mpc8548cds.dtb\0" 513 514 #define CONFIG_NFSBOOTCOMMAND \ 515 "setenv bootargs root=/dev/nfs rw " \ 516 "nfsroot=$serverip:$rootpath " \ 517 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 518 "console=$consoledev,$baudrate $othbootargs;" \ 519 "tftp $loadaddr $bootfile;" \ 520 "tftp $fdtaddr $fdtfile;" \ 521 "bootm $loadaddr - $fdtaddr" 522 523 #define CONFIG_RAMBOOTCOMMAND \ 524 "setenv bootargs root=/dev/ram rw " \ 525 "console=$consoledev,$baudrate $othbootargs;" \ 526 "tftp $ramdiskaddr $ramdiskfile;" \ 527 "tftp $loadaddr $bootfile;" \ 528 "tftp $fdtaddr $fdtfile;" \ 529 "bootm $loadaddr $ramdiskaddr $fdtaddr" 530 531 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 532 533 #endif /* __CONFIG_H */ 534