1 /* 2 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_SYS_SRIO 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 19 #define CONFIG_PCI1 /* PCI controller 1 */ 20 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 21 #undef CONFIG_PCI2 22 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 23 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 24 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 26 27 #define CONFIG_ENV_OVERWRITE 28 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 29 30 #define CONFIG_FSL_VIA 31 32 #ifndef __ASSEMBLY__ 33 extern unsigned long get_clock_freq(void); 34 #endif 35 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 36 37 /* 38 * These can be toggled for performance analysis, otherwise use default. 39 */ 40 #define CONFIG_L2_CACHE /* toggle L2 cache */ 41 #define CONFIG_BTB /* toggle branch predition */ 42 43 /* 44 * Only possible on E500 Version 2 or newer cores. 45 */ 46 #define CONFIG_ENABLE_36BIT_PHYS 1 47 48 #ifdef CONFIG_PHYS_64BIT 49 #define CONFIG_ADDR_MAP 50 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 51 #endif 52 53 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 54 #define CONFIG_SYS_MEMTEST_END 0x00400000 55 56 #define CONFIG_SYS_CCSRBAR 0xe0000000 57 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 58 59 /* DDR Setup */ 60 #undef CONFIG_FSL_DDR_INTERACTIVE 61 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 62 #define CONFIG_DDR_SPD 63 64 #define CONFIG_DDR_ECC 65 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 66 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 67 68 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 70 71 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 72 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 73 74 /* I2C addresses of SPD EEPROMs */ 75 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 76 77 /* Make sure required options are set */ 78 #ifndef CONFIG_SPD_EEPROM 79 #error ("CONFIG_SPD_EEPROM is required") 80 #endif 81 82 #undef CONFIG_CLOCKS_IN_MHZ 83 /* 84 * Physical Address Map 85 * 86 * 32bit: 87 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 88 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 89 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 90 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 91 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 92 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 93 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 94 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 95 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 96 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 97 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 98 * 99 * 36bit: 100 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 101 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 102 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 103 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 104 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 105 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 106 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 107 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 108 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 109 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 110 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 111 * 112 */ 113 114 /* 115 * Local Bus Definitions 116 */ 117 118 /* 119 * FLASH on the Local Bus 120 * Two banks, 8M each, using the CFI driver. 121 * Boot from BR0/OR0 bank at 0xff00_0000 122 * Alternate BR1/OR1 bank at 0xff80_0000 123 * 124 * BR0, BR1: 125 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 126 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 127 * Port Size = 16 bits = BRx[19:20] = 10 128 * Use GPCM = BRx[24:26] = 000 129 * Valid = BRx[31] = 1 130 * 131 * 0 4 8 12 16 20 24 28 132 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 133 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 134 * 135 * OR0, OR1: 136 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 137 * Reserved ORx[17:18] = 11, confusion here? 138 * CSNT = ORx[20] = 1 139 * ACS = half cycle delay = ORx[21:22] = 11 140 * SCY = 6 = ORx[24:27] = 0110 141 * TRLX = use relaxed timing = ORx[29] = 1 142 * EAD = use external address latch delay = OR[31] = 1 143 * 144 * 0 4 8 12 16 20 24 28 145 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 146 */ 147 148 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 149 #ifdef CONFIG_PHYS_64BIT 150 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 151 #else 152 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 153 #endif 154 155 #define CONFIG_SYS_BR0_PRELIM \ 156 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 157 #define CONFIG_SYS_BR1_PRELIM \ 158 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 159 160 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 161 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 162 163 #define CONFIG_SYS_FLASH_BANKS_LIST \ 164 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 165 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 166 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 167 #undef CONFIG_SYS_FLASH_CHECKSUM 168 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 170 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 172 173 #define CONFIG_FLASH_CFI_DRIVER 174 #define CONFIG_SYS_FLASH_CFI 175 #define CONFIG_SYS_FLASH_EMPTY_INFO 176 177 #define CONFIG_HWCONFIG /* enable hwconfig */ 178 179 /* 180 * SDRAM on the Local Bus 181 */ 182 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 183 #ifdef CONFIG_PHYS_64BIT 184 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 185 #else 186 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 187 #endif 188 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 189 190 /* 191 * Base Register 2 and Option Register 2 configure SDRAM. 192 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 193 * 194 * For BR2, need: 195 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 196 * port-size = 32-bits = BR2[19:20] = 11 197 * no parity checking = BR2[21:22] = 00 198 * SDRAM for MSEL = BR2[24:26] = 011 199 * Valid = BR[31] = 1 200 * 201 * 0 4 8 12 16 20 24 28 202 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 203 * 204 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 205 * FIXME: the top 17 bits of BR2. 206 */ 207 208 #define CONFIG_SYS_BR2_PRELIM \ 209 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 210 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 211 212 /* 213 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 214 * 215 * For OR2, need: 216 * 64MB mask for AM, OR2[0:7] = 1111 1100 217 * XAM, OR2[17:18] = 11 218 * 9 columns OR2[19-21] = 010 219 * 13 rows OR2[23-25] = 100 220 * EAD set for extra time OR[31] = 1 221 * 222 * 0 4 8 12 16 20 24 28 223 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 224 */ 225 226 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 227 228 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 229 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 230 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 231 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 232 233 /* 234 * Common settings for all Local Bus SDRAM commands. 235 * At run time, either BSMA1516 (for CPU 1.1) 236 * or BSMA1617 (for CPU 1.0) (old) 237 * is OR'ed in too. 238 */ 239 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 240 | LSDMR_PRETOACT7 \ 241 | LSDMR_ACTTORW7 \ 242 | LSDMR_BL8 \ 243 | LSDMR_WRC4 \ 244 | LSDMR_CL3 \ 245 | LSDMR_RFEN \ 246 ) 247 248 /* 249 * The CADMUS registers are connected to CS3 on CDS. 250 * The new memory map places CADMUS at 0xf8000000. 251 * 252 * For BR3, need: 253 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 254 * port-size = 8-bits = BR[19:20] = 01 255 * no parity checking = BR[21:22] = 00 256 * GPMC for MSEL = BR[24:26] = 000 257 * Valid = BR[31] = 1 258 * 259 * 0 4 8 12 16 20 24 28 260 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 261 * 262 * For OR3, need: 263 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 264 * disable buffer ctrl OR[19] = 0 265 * CSNT OR[20] = 1 266 * ACS OR[21:22] = 11 267 * XACS OR[23] = 1 268 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 269 * SETA OR[28] = 0 270 * TRLX OR[29] = 1 271 * EHTR OR[30] = 1 272 * EAD extra time OR[31] = 1 273 * 274 * 0 4 8 12 16 20 24 28 275 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 276 */ 277 278 #define CONFIG_FSL_CADMUS 279 280 #define CADMUS_BASE_ADDR 0xf8000000 281 #ifdef CONFIG_PHYS_64BIT 282 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 283 #else 284 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 285 #endif 286 #define CONFIG_SYS_BR3_PRELIM \ 287 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 288 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 289 290 #define CONFIG_SYS_INIT_RAM_LOCK 1 291 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 292 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 293 294 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 295 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 296 297 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 298 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 299 300 /* Serial Port */ 301 #define CONFIG_SYS_NS16550_SERIAL 302 #define CONFIG_SYS_NS16550_REG_SIZE 1 303 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 304 305 #define CONFIG_SYS_BAUDRATE_TABLE \ 306 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 307 308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 310 311 /* 312 * I2C 313 */ 314 #define CONFIG_SYS_I2C 315 #define CONFIG_SYS_I2C_FSL 316 #define CONFIG_SYS_FSL_I2C_SPEED 400000 317 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 318 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 319 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 320 321 /* EEPROM */ 322 #define CONFIG_ID_EEPROM 323 #define CONFIG_SYS_I2C_EEPROM_CCID 324 #define CONFIG_SYS_ID_EEPROM 325 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 326 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 327 328 /* 329 * General PCI 330 * Memory space is mapped 1-1, but I/O space must start from 0. 331 */ 332 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 333 #ifdef CONFIG_PHYS_64BIT 334 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 335 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 336 #else 337 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 338 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 339 #endif 340 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 341 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 342 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 343 #ifdef CONFIG_PHYS_64BIT 344 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 345 #else 346 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 347 #endif 348 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 349 350 #ifdef CONFIG_PCIE1 351 #define CONFIG_SYS_PCIE1_NAME "Slot" 352 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 355 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 356 #else 357 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 358 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 359 #endif 360 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 361 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 362 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 365 #else 366 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 367 #endif 368 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 369 #endif 370 371 /* 372 * RapidIO MMU 373 */ 374 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 375 #ifdef CONFIG_PHYS_64BIT 376 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 377 #else 378 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 379 #endif 380 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 381 382 #ifdef CONFIG_LEGACY 383 #define BRIDGE_ID 17 384 #define VIA_ID 2 385 #else 386 #define BRIDGE_ID 28 387 #define VIA_ID 4 388 #endif 389 390 #if defined(CONFIG_PCI) 391 #undef CONFIG_EEPRO100 392 #undef CONFIG_TULIP 393 394 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 395 396 #endif /* CONFIG_PCI */ 397 398 #if defined(CONFIG_TSEC_ENET) 399 400 #define CONFIG_MII 1 /* MII PHY management */ 401 #define CONFIG_TSEC1 1 402 #define CONFIG_TSEC1_NAME "eTSEC0" 403 #define CONFIG_TSEC2 1 404 #define CONFIG_TSEC2_NAME "eTSEC1" 405 #define CONFIG_TSEC3 1 406 #define CONFIG_TSEC3_NAME "eTSEC2" 407 #define CONFIG_TSEC4 408 #define CONFIG_TSEC4_NAME "eTSEC3" 409 #undef CONFIG_MPC85XX_FEC 410 411 #define CONFIG_PHY_MARVELL 412 413 #define TSEC1_PHY_ADDR 0 414 #define TSEC2_PHY_ADDR 1 415 #define TSEC3_PHY_ADDR 2 416 #define TSEC4_PHY_ADDR 3 417 418 #define TSEC1_PHYIDX 0 419 #define TSEC2_PHYIDX 0 420 #define TSEC3_PHYIDX 0 421 #define TSEC4_PHYIDX 0 422 #define TSEC1_FLAGS TSEC_GIGABIT 423 #define TSEC2_FLAGS TSEC_GIGABIT 424 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 425 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 426 427 /* Options are: eTSEC[0-3] */ 428 #define CONFIG_ETHPRIME "eTSEC0" 429 #endif /* CONFIG_TSEC_ENET */ 430 431 /* 432 * Environment 433 */ 434 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 435 #define CONFIG_ENV_ADDR 0xfff80000 436 #else 437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 438 #endif 439 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 440 #define CONFIG_ENV_SIZE 0x2000 441 442 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 444 445 /* 446 * BOOTP options 447 */ 448 #define CONFIG_BOOTP_BOOTFILESIZE 449 450 #undef CONFIG_WATCHDOG /* watchdog disabled */ 451 452 /* 453 * Miscellaneous configurable options 454 */ 455 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 456 457 /* 458 * For booting Linux, the board info and command line data 459 * have to be in the first 64 MB of memory, since this is 460 * the maximum mapped by the Linux kernel during initialization. 461 */ 462 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 463 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 464 465 #if defined(CONFIG_CMD_KGDB) 466 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 467 #endif 468 469 /* 470 * Environment Configuration 471 */ 472 #if defined(CONFIG_TSEC_ENET) 473 #define CONFIG_HAS_ETH0 474 #define CONFIG_HAS_ETH1 475 #define CONFIG_HAS_ETH2 476 #define CONFIG_HAS_ETH3 477 #endif 478 479 #define CONFIG_IPADDR 192.168.1.253 480 481 #define CONFIG_HOSTNAME "unknown" 482 #define CONFIG_ROOTPATH "/nfsroot" 483 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 484 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 485 486 #define CONFIG_SERVERIP 192.168.1.1 487 #define CONFIG_GATEWAYIP 192.168.1.1 488 #define CONFIG_NETMASK 255.255.255.0 489 490 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 491 492 #define CONFIG_EXTRA_ENV_SETTINGS \ 493 "hwconfig=fsl_ddr:ecc=off\0" \ 494 "netdev=eth0\0" \ 495 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 496 "tftpflash=tftpboot $loadaddr $uboot; " \ 497 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 498 " +$filesize; " \ 499 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 500 " +$filesize; " \ 501 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 502 " $filesize; " \ 503 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 504 " +$filesize; " \ 505 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 506 " $filesize\0" \ 507 "consoledev=ttyS1\0" \ 508 "ramdiskaddr=2000000\0" \ 509 "ramdiskfile=ramdisk.uboot\0" \ 510 "fdtaddr=1e00000\0" \ 511 "fdtfile=mpc8548cds.dtb\0" 512 513 #define CONFIG_NFSBOOTCOMMAND \ 514 "setenv bootargs root=/dev/nfs rw " \ 515 "nfsroot=$serverip:$rootpath " \ 516 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 517 "console=$consoledev,$baudrate $othbootargs;" \ 518 "tftp $loadaddr $bootfile;" \ 519 "tftp $fdtaddr $fdtfile;" \ 520 "bootm $loadaddr - $fdtaddr" 521 522 #define CONFIG_RAMBOOTCOMMAND \ 523 "setenv bootargs root=/dev/ram rw " \ 524 "console=$consoledev,$baudrate $othbootargs;" \ 525 "tftp $ramdiskaddr $ramdiskfile;" \ 526 "tftp $loadaddr $bootfile;" \ 527 "tftp $fdtaddr $fdtfile;" \ 528 "bootm $loadaddr $ramdiskaddr $fdtaddr" 529 530 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 531 532 #endif /* __CONFIG_H */ 533